-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
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-- notice that this model has been modified and the date of modification; and 
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-- conspicuous notice that this model is available from Mentor Graphics in its
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--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
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-------------------------------------------------------------------------------
-- File       : d2a_nbit.vhd
-- Author     : Mentor Graphics
-- Created    : 2001/12/03
-- Last update: 2003-05-13
-------------------------------------------------------------------------------
-- Description: Variable-bit D/A converter
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2001/12/03  1.0         Mentor Graphics     Created    
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.electrical_systems.all;

entity d2a_nbit is

  generic (
    vmax     : voltage    := 5.0;          -- High output
    vmin     : voltage    := 0.0;          -- Low output
    high_bit : integer := 9;            -- High end of bit range for D/A
    low_bit  : integer := 0);           -- Low end of bit range for D/A

  port (
    signal   bus_in  : in std_logic_vector;  -- variable width vector input
    signal   latch   : in std_logic;
    terminal ana_out : electrical);       -- analog output

end entity d2a_nbit;

architecture behavioral of d2a_nbit is
  signal   sout : real := 0.0;
  quantity vout across iout through ana_out to electrical_ref;
begin

  proc : process
    variable v_sum  : voltage;   -- Sum of voltage contribution from each bit
    variable delt_v : voltage;   -- Represents the voltage value of each bit
  begin
    wait until (latch'event and latch = '1');  -- Begin when latch goes high
    v_sum  := vmin;
    delt_v := vmax - vmin;
    for i in high_bit downto low_bit loop  -- Perform the conversions
      delt_v  := delt_v / 2.0;
      if bus_in(i) = '1' or bus_in(i) = 'H' then
        v_sum := v_sum + delt_v;
      end if;
    end loop;
    sout <= v_sum;
  end process;

  vout == sout'ramp(100.0E-9);   -- Ensure continuous transition between levels

end architecture behavioral;

-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------