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-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
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-- File       : switch_dig_2in.vhd
-- Author     : Mentor Graphics
-- Created    : 2003/04/21
-- Last update: 2003-05-13
-------------------------------------------------------------------------------
-- Description: Two input analog switch 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003/04/21  1.0         Mentor Graphics     Created    
--------------------------------------------------------------------------------- 

-- Simple Digital-Controlled Two-position Switch Model
-- Switch position 1 ('0') or switch position 2 ('1')

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.electrical_systems.all;

entity switch_dig_2in is
  generic (r_open     : RESISTANCE := 1.0e6;     -- Open switch resistance
           r_closed   : RESISTANCE := 0.001;     -- Closed switch resistance
           trans_time : real       := 0.00001);  -- Transition time to each position

  port (sw_state                     : in std_logic;  -- Digital control input 
        terminal p_in1, p_in2, p_out :    ELECTRICAL);  -- Analog output
end entity switch_dig_2in;

architecture ideal of switch_dig_2in is
  signal r_sig1 : RESISTANCE := r_closed;  -- switch1 resistance signal
  signal r_sig2 : RESISTANCE := r_open;  -- switch1 resistance signal
  quantity v1 across i1 through p_in1 to p_out;  -- V & I for in1 to out
  quantity v2 across i2 through p_in2 to p_out;  -- V & I for in2 to out
  quantity r1     : RESISTANCE;  -- Time-varying resistance for in1 to out
  quantity r2     : RESISTANCE;  -- Time-varying resistance for in2 to out
begin
  process (sw_state)                    -- Sensitivity to digital control input
  begin
    if (sw_state = '0') then            -- Close sig1, open sig2
      r_sig1 <= r_closed;
      r_sig2 <= r_open;
    elsif (sw_state = '1') then         -- Open sig1, close sig2
      r_sig1 <= r_open;
      r_sig2 <= r_closed;
    end if;
  end process;
  r1 == r_sig1'RAMP(trans_time, trans_time);  -- Ensure resistance continuity
  r2 == r_sig2'RAMP(trans_time, trans_time);  -- Ensure resistance continuity
  v1 == r1*i1;                          -- Apply Ohm's law to in1
  v2 == r2*i2;                          -- Apply Ohm's law to in2
end architecture ideal;

-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------