-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except 
-- compilations distributed in accordance with Section (d) of this license 
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such 
-- version is modified; (c) any modified version must include a conspicuous 
-- notice that this model has been modified and the date of modification; and 
-- (d) any compilations sold by you that include this model must include a 
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File       : wire.vhd
-- Author     : Mentor Graphics
-- Created    : 2002-08-14
-- Last update: 2002-08-14
-------------------------------------------------------------------------------
-- Description: Simple wire model with current direction monitor
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2002-08-14  1.0         Mentor Graphics     Created    
-------------------------------------------------------------------------------

-- Internal package for setting up enumerated list of wire gauge types
package wire_package is
  type wire_gauge is (awg10, awg12, awg14, awg16, awg18, awg20, awg22, awg24);
  function wire_resistance_select (selection : in wire_gauge)
    return real;
end package wire_package;

package body wire_package is  
  function wire_resistance_select (selection : in wire_gauge)
    return real is
  begin
    case selection is
      when awg10 => return 0.00328;     -- Resistance (Ohms per meter)
      when awg12 => return 0.00521;
      when awg14 => return 0.00828;
      when awg16 => return 0.0132;
      when awg18 => return 0.0209;
      when awg20 => return 0.0332;
      when awg22 => return 0.0527;
      when awg24 => return 0.0842;
    end case;
  end function wire_resistance_select;
end package body wire_package;

-- Begin wire model
library IEEE;
use IEEE.electrical_systems.all;
use work.wire_package.all;

entity wire is
  generic (
    gauge : wire_gauge := awg10;              -- Select Wire Gauge
                                              -- [awg10,awg12, ... awg24]
    length : real       := 1.0;               -- Wire length [meters]
    i_reverse_detect : current := 100.0e-3);  -- Reverse current level
                                              -- detection threshold [Amps]
  port (
    terminal p, m : electrical);
end entity wire;


architecture directional of wire is
  quantity v across i through p to m;
  constant r : real := wire_resistance_select(gauge);

  type   current_direction is (forward, reverse);
  signal current_monitor : current_direction := forward;  -- Current monitor
                                                          -- state

begin  
  monitor : process
  begin
    --  wait until domain = time_domain;  
    wait until not i'ABOVE(-1.0*i_reverse_detect);
    current_monitor <= reverse;
    report " Current Reversal Detected - Possible Sneak Circuit ";
    wait;                               -- Forever
  end process monitor;

  v == i*r*length; 

end architecture directional;

-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------