library IEEE; 
use ieee.std_logic_1164.all;
use ieee.electrical_systems.all;
LIBRARY edulib;
USE work.all

entity tb_2in_switch is
end tb_2in_switch;

architecture TB_2in_switch of tb_2in_switch is
    -- Component declarations

  component V_CONSTANT
      generic( AC_MAG : VOLTAGE:=0.0;
               AC_PHASE : REAL:=0.0;
               LEVEL : VOLTAGE );
      port( terminal POS :  ELECTRICAL;
            terminal NEG :  ELECTRICAL );
   end component V_CONSTANT;

	component clock
		generic (period: time;
				duty: real := 0.5);
		port ( signal clk_out : std_logic);
	end component clock;

	component resistor
		generic (res : resistance);
		port (terminal p1: electrical;
			terminal p2: electrical);
	end component resistor;

	component switch_dig_2in
		port (terminal p_in1, p_in2, p_out: electrical;
		signal sw_state: std_ulogic);
	end component resistor;

    -- Signal declarations
    terminal p_in1, p_in2, p_out : electrical;
	signal ctl_ulogic : std_ulogic;
    signal ctl_logic : std_logic;

	for vdc1:v_constant use entity edulib.v_constant;
	for vdc2:v_constant use entity edulib.v_constant;
	for clk1:clock use entity edulib.clock;
	for R1:resistor use entity edulib.resistor(ideal);
	for swtch:switch_dig_2in use entity work.switch_dig_2in;

begin
    -- Signal assignments
	ctl_ulogic <= To_X01(ctl_logic); -- Convert X01Z to X01
    -- Component instances
    vdc1 : entity work.v_constant(ideal)
        generic map(
            level => 1.0
        )
        port map(
            pos => p_in1,
            neg => ELECTRICAL_REF
        );
    vdc2 : entity work.v_constant(ideal)
        generic map(
            level => 3.0
        )
        port map(
            pos => p_in2,
            neg => ELECTRICAL_REF
        );
    clk1 : entity work.clock(ideal)
        generic map(
            period => 10.0ms
        )        
		port map(
            clk_out => ctl_logic
        );
    R1 : entity work.resistor(ideal)
        generic map(
            res => 100.0
        )        
		port map(
            p1 => p_out,
            p2 => electrical_ref
        );
    swtch : entity work.switch_dig_2in(ideal)
        port map(
            p_in1 => p_in1,
            p_in2 => p_in2,
		p_out => p_out,
		sw_state => ctl_ulogic
        );
end TB_2in_switch;