library IEEE; 
use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
use IEEE.electrical_systems.all;

entity tb_a2d_d2a is
end tb_a2d_d2a;

architecture TB_a2d_d2a of tb_a2d_d2a is
    -- Component declarations
    -- Signal declarations
	terminal ana_out : electrical;
	terminal analog_in : electrical;
	signal clock : std_ulogic;
	signal start : std_ulogic;
	signal eoc : std_ulogic;
	signal eoc_logic: std_logic;
	signal oe : std_logic;
	signal data_bus : std_ulogic_vector(0 to 9);
	signal latch : std_ulogic;
	signal latch_logic : std_logic;
	signal nn_eoc : std_logic;
	signal or_out : std_logic;
	signal n_eoc : std_logic;

   component A2D_NBIT
      port( terminal AIN :  ELECTRICAL;
            signal CLK : IN STD_LOGIC;
            signal DOUT : OUT STD_LOGIC_VECTOR(0 to 9);
            signal EOC : OUT STD_LOGIC;
            signal OE : IN STD_LOGIC;
            signal START : IN STD_LOGIC );
   end component A2D_NBIT;

   component V_SINE
      generic( AC_MAG : VOLTAGE:=0.0;
               AC_PHASE : REAL:=0.0;
               AMPLITUDE : VOLTAGE;
               DF : REAL:=0.0;
               FREQ : REAL;
               OFFSET : VOLTAGE:=0.0;
               PHASE : REAL:=0.0 );
      port( terminal POS :  ELECTRICAL;
            terminal NEG :  ELECTRICAL );
   end component V_SINE;

   component INVERTER
      generic( DELAY : TIME:=0 NS );
      port( signal INPUT : IN STD_LOGIC;
            signal OUTPUT : OUT STD_LOGIC );
   end component INVERTER;

   component BUFF
      generic( DELAY : TIME:=0 NS );
      port( signal INPUT : IN STD_LOGIC;
            signal OUTPUT : OUT STD_LOGIC );
   end component BUFF;

   component OR2
      generic( DELAY : TIME:=0 NS );
      port( signal IN1 : IN STD_LOGIC;
            signal IN2 : IN STD_LOGIC;
            signal OUTPUT : OUT STD_LOGIC );
   end component OR2;

   component D2A_10_BIT
      generic( HIGH_BIT : INTEGER:=9;
               LOW_BIT : INTEGER:=0;
               VMAX : REAL:=5.0;
               VMIN : REAL:=0.0 );
      port( signal BUS_IN : IN STD_LOGIC_VECTOR(0 to 11);
            signal LATCH : IN STD_LOGIC;
            terminal ANA_OUT :  ELECTRICAL );
   end component D2A_10_BIT;

   for da1: DAC_10_BIT use entity WORK.DAC_10_BIT(behavioral);
   for or1: OR2 use entity WORK.OR2;
   for U2: buff use entity WORK.buff;
   for INV1: INVERTER use entity WORK.INVERTER;
   for INV2: INVERTER use entity WORK.INVERTER;
   for INV3: INVERTER use entity WORK.INVERTER;
   for v1: v_sine use entity work.v_sine;
   for ad1: a2d_nbit use entity EDULIB.a2d_nbit;

begin
    -- Signal assignments
	eoc_logic <= To_X01Z(eoc);	-- convert std_ulogic to std_logic
	latch <= To_X01(latch_logic);	-- convert std_logic to std_ulogic
    -- Component instances
    ad1 : entity work.a2d_nbit(sar)
        port map(
            dout => data_bus,
            ain => analog_in,
            clk => clock,
            start => start,
            eoc => eoc
        );
    v1 : entity work.v_sine(ideal)
        generic map(
            freq => 2.5,
            amplitude => 2.5,
			offset => 2.5,
            phase => 0.0
        )
        port map(
            pos => analog_in,
            neg => ELECTRICAL_REF
        );
    inv1 : entity work.inverter(ideal)
        generic map(
            delay => 2 us
        )
        port map(
            input => or_out,
            output => oe
        );
    inv2 : entity work.inverter(ideal)
        generic map(
            delay => 2 us
        )
        port map(
            input => n_eoc,
            output => nn_eoc
        );
    or1 : entity work.or2(ideal)
        port map(
            in1 => n_eoc,
            in2 => nn_eoc,
            output => or_out
        );
    inv3 : entity work.inverter(ideal)
        generic map(
            delay => 0 us
        )
        port map(
            input => eoc_logic,
            output => n_eoc
        );
    U2 : entity work.buff(ideal)
        generic map(
            delay => 250 ns
        )
        port map(
            input => oe,
            output => latch_logic
        );
    da1 : entity work.dac_10_bit(behavioral)
        port map(
            bus_in => data_bus,
            analog_out => ana_out,
            clk => latch
        );
  -- clock
    P_clock :
    process
    begin
        clock <= '1';
        wait for 50.0 us;
        clock <= '0';
        wait for 50.0 us;
    end process P_clock;

  -- start
    P_start :
    process
    begin
        start <= '0';
        wait for 2.0 ms;
        start <= '1';
        wait for 0.2 ms;
        start <= '0';
        wait for 2.0 ms;
    end process P_start;


end TB_a2d_d2a;