-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
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-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
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-------------------------------------------------------------------------------
-- File       : Lead_Lag_Diff.vhd
-- Author     : Mentor Graphics
-- Created    : 2002/05/21
-- Last update: 2002/05/21
-------------------------------------------------------------------------------
-- Description: Z-domain Lead-Lag Compensator with electrical connections. 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2002/05/21  1.0         Mentor Graphics     Created    
-------------------------------------------------------------------------------

library IEEE; use IEEE.std_logic_1164.all; use IEEE.math_real.all;
library IEEE; use IEEE.electrical_systems.all;

entity Lead_Lag_Diff is
	generic (	fp : real := 2000.0;	-- Pole in Hz for 'ztf
				fz : real := 5.0;	-- Zero in Hz for 'ztf
				k : real := 400.0;  -- Normalizing gain
				Fsmp : real := 10.0e3);	-- Sample frequency for 'ztf 
	port 	(	signal clk : in std_logic; -- Clock is used for the Difference equations only
				terminal input: electrical;
				terminal output: electrical);
end entity Lead_Lag_Diff ;

-------------------------------------------------------------------------------
-- Difference Equation:
--
--	Y(K) = k_diff*[AX(k) - BX(k-1) + CY(k-1)]
-------------------------------------------------------------------------------
architecture diff of Lead_Lag_Diff is
  quantity vin across input to ELECTRICAL_REF;
  quantity vout across iout through output to ELECTRICAL_REF;
  constant A : real := 0.6163507; -- current input coefficient
  constant B : real := 0.6144184; -- delayed input coefficient
  constant C : real := 0.2307692; -- delayed output coefficient
  
signal z_out : real := 0.0;
begin
proc : process (clk)

	variable zi_dly1 : real := 0.0; -- Input delayed 1 clk cycle
	variable zo_dly1 : real := 0.0; -- Output delayed 1 clk cycle
	variable z_new : real := 0.0;	-- New output value this clk cycle

 	begin  -- proc
		zo_dly1 := z_out; -- Store previous output value
		z_new := A*vin - B*zi_dly1 + C*zo_dly1;
		zi_dly1 := vin; -- Store previous input value
		z_out <= z_new;
	end process;
	vout == k*z_out'ramp(100.0e-9); -- Ensure continuous transitions on output
end diff;