------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : Lead_Lag_Ztf.vhd -- Author : Mentor Graphics -- Created : 2002/05/21 -- Last update: 2002/05/21 ------------------------------------------------------------------------------- -- Description: Z-domain Lead-Lag Compensator with electrical connections. ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2002/05/21 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.math_real.all; library IEEE; use IEEE.electrical_systems.all; entity Lead_Lag_Ztf is generic ( fp : real := 2000.0; -- Pole in Hz for 'ztf fz : real := 5.0; -- Zero in Hz for 'ztf k : real := 400.0; -- Normalizing gain Fsmp : real := 10.0e3); -- Sample frequency for 'ztf port ( signal clk : in std_logic; -- Clock is used for the Difference equations only terminal input: electrical; terminal output: electrical); end entity Lead_Lag_Ztf; ------------------------------------------------------------------------------- -- Transfer Function is derived from the following using the bilinear transform: -- -- 1 + (s/wz) -- H(s) = K * ------------ -- 1 + (s/wp) -- ------------------------------------------------------------------------------- architecture ztf of Lead_Lag_Ztf is QUANTITY vin ACROSS input TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; constant T : real := 1.0/Fsmp; -- Sample period constant wz : real := fz*math_2_pi; -- Pole in rad/s constant wp : real := fp*math_2_pi; -- Pole in rad/s constant n0 : real := 2.0 + T*wz; -- z0 numerator coefficient constant n1 : real := T*wz - 2.0; -- z-1 numerator coefficient constant d0 : real := 2.0 + T*wp; -- z0 denominator coefficient constant d1 : real := T*wp - 2.0; -- z-1 denominator coefficient constant num : real_vector := (n0, n1); constant den : real_vector := (d0, d1); begin -- ztf vout == k*vin'Ztf(num,den,T); end ztf;