-- C:\Mentor_Projects\CS2_Mixed_Technology\hdl\clock.vhd
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except 
-- compilations distributed in accordance with Section (d) of this license 
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such 
-- version is modified; (c) any modified version must include a conspicuous 
-- notice that this model has been modified and the date of modification; and 
-- (d) any compilations sold by you that include this model must include a 
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File       : clock.vhd
-- Author     : Mentor Graphics
-- Created    : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Digital clock with 50% duty cycle
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2001/06/16  1.0         Mentor Graphics     Created    
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity clock is
  generic (
    period : time);                     -- Clock period

  port (
    clk_out : out std_logic);

end entity clock;

architecture ideal of clock is

begin
  CreateClock: process 
  begin
    clk_out <= '0';
    wait for period/2;
    clk_out <= '1';
    wait for period/2;   
  end process CreateClock;

end architecture ideal;


-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--

-- C:\Mentor_Projects\CS2_Mixed_Technology\hdl\rot2v.vhd
-------------------------------------------------------------------------------
-- Rotational to Electrical Converter
--
-------------------------------------------------------------------------------

-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE;
use IEEE.mechanical_systems.all;
use IEEE.electrical_systems.all;

entity rot2v is
  
  generic (
    k : real := 1.0);                -- optional gain

  port (
    terminal input   : rotational;  -- input terminal
    terminal output    : electrical);   -- output terminal
  
end entity rot2v ;

architecture bhv of rot2v is
quantity rot_in across input to rotational_ref;     -- Converter's input branch
quantity v_out across out_i through output to electrical_ref;-- Converter's output branch

  begin  -- bhv
   v_out ==  k*rot_in; 
end bhv;
--

-- C:\Mentor_Projects\CS2_Mixed_Technology\hdl\gear_rv_r.vhd
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except 
-- compilations distributed in accordance with Section (d) of this license 
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such 
-- version is modified; (c) any modified version must include a conspicuous 
-- notice that this model has been modified and the date of modification; and 
-- (d) any compilations sold by you that include this model must include a 
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File       : gear_rv_r.vhd
-- Author     : Mentor Graphics
-- Created    : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2001/10/10  1.0         Mentor Graphics     Created    
-------------------------------------------------------------------------------

-- Use proposed IEEE natures and packages
library IEEE;
use IEEE.mechanical_systems.all;

entity gear_rv_r is

  generic(
    ratio : real := 1.0);   -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
                            -- Note: can be negative, if shaft polarity changes

  port ( terminal rotv1 : ROTATIONAL_VELOCITY;
  		terminal rot2 : rotational);

end entity gear_rv_r;

-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of gear_rv_r is

  quantity w1 across torq_vel through rotv1 to ROTATIONAL_VELOCITY_REF;
--  quantity w2 across torq2 through rotv2 to rotational_v_ref;
  quantity theta across torq_ang through rot2 to rotational_ref;

begin

--  w2  == w1*ratio;
  theta == ratio*w1'integ;
  torq_vel == -1.0*torq_ang*ratio;

end architecture ideal;

-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--

-- C:\Mentor_Projects\CS2_Mixed_Technology\hdl\lead_lag_ztf_diff.vhd
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except 
-- compilations distributed in accordance with Section (d) of this license 
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such 
-- version is modified; (c) any modified version must include a conspicuous 
-- notice that this model has been modified and the date of modification; and 
-- (d) any compilations sold by you that include this model must include a 
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File       : Lead_Lag_Ztf_Diff.vhd
-- Author     : Mentor Graphics
-- Created    : 2002/05/21
-- Last update: 2002/05/21
-------------------------------------------------------------------------------
-- Description: Z-domain Lead-Lag Compensator with electrical connections. 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2002/05/21  1.0         Mentor Graphics     Created    
-------------------------------------------------------------------------------

library IEEE; use IEEE.std_logic_1164.all; use IEEE.math_real.all;
library IEEE; use IEEE.electrical_systems.all;

entity Lead_Lag_Ztf_Diff is
	generic (	fp : real := 2000.0;	-- Pole in Hz for 'ztf
				fz : real := 5.0;	-- Zero in Hz for 'ztf
				k : real := 400.0;  -- Normalizing gain
				Fsmp : real := 10.0e3);	-- Sample frequency for 'ztf 
	port 	(	signal clk : in std_logic; -- Clock is used for the Difference equations only
				terminal input: electrical;
				terminal output: electrical);
end entity Lead_Lag_Ztf_Diff ;
-------------------------------------------------------------------------------
-- Transfer Function is derived from the following using the bilinear transform:
--
--              1 + (s/wz)
--  H(s) = K * ------------
--              1 + (s/wp)
-- 
-------------------------------------------------------------------------------
architecture ztf of Lead_Lag_Ztf_Diff is
	QUANTITY vin ACROSS input TO ELECTRICAL_REF;
	QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
	constant T : real := 1.0/Fsmp;	-- Sample period
	constant wz : real := fz*math_2_pi;	-- Pole in rad/s
	constant wp : real := fp*math_2_pi;	-- Pole in rad/s
	constant n0 : real := 2.0 + T*wz; 	-- z0 numerator coefficient
	constant n1 : real := T*wz - 2.0; 	-- z-1 numerator coefficient
	constant d0 : real := 2.0 + T*wp; 	-- z0 denominator coefficient
	constant d1 : real := T*wp - 2.0; 	-- z-1 denominator coefficient
	constant num : real_vector := (n0, n1); 
	constant den : real_vector := (d0, d1);
begin	-- ztf
	vout == k*vin'Ztf(num,den,T);   
end ztf;

-------------------------------------------------------------------------------
-- Difference Equation:
--
--	Y(K) = k_diff*[AX(k) - BX(k-1) + CY(k-1)]
-------------------------------------------------------------------------------
architecture diff of Lead_Lag_Ztf_Diff is
  quantity vin across input to ELECTRICAL_REF;
  quantity vout across iout through output to ELECTRICAL_REF;
  constant A : real := 0.6163507; -- current input coefficient
  constant B : real := 0.6144184; -- delayed input coefficient
  constant C : real := 0.2307692; -- delayed output coefficient
  
signal z_out : real := 0.0;
begin
proc : process (clk)

	variable zi_dly1 : real := 0.0; -- Input delayed 1 clk cycle
	variable zo_dly1 : real := 0.0; -- Output delayed 1 clk cycle
	variable z_new : real := 0.0;	-- New output value this clk cycle

 	begin  -- proc
		zo_dly1 := z_out; -- Store previous output value
		z_new := A*vin - B*zi_dly1 + C*zo_dly1;
		zi_dly1 := vin; -- Store previous input value
		z_out <= z_new;
	end process;
	vout == k*z_out'ramp(100.0e-9); -- Ensure continuous transitions on output
end diff;
--

-- C:\Mentor_Projects\CS2_Mixed_Technology\hdl\limiter_2_e.vhd
library IEEE; use IEEE.electrical_systems.all;
entity limiter_2_e is
	generic (
		limit_high : real := 4.8;	-- upper limit
		limit_low : real := -4.8); 	-- lower limit
	port (
		terminal input: electrical;
		terminal output: electrical);					
end entity limiter_2_e;

architecture simple of limiter_2_e is
  	QUANTITY vin ACROSS input TO ELECTRICAL_REF;
  	QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
	constant slope : real := 1.0e-4;
begin
	if vin > limit_high use	-- Upper limit exceeded, so limit input signal
		vout == limit_high + slope*(vin - limit_high);
	elsif vin < limit_low use	-- Lower limit exceeded, so limit input signal
		vout == limit_low + slope*(vin - limit_low);
	else		-- No limit exceeded, so pass input signal as is
		vout == vin;
	end use;
	break on vin'above(limit_high), vin'above(limit_low);
end architecture simple;
--

-- C:\Mentor_Projects\CS2_Mixed_Technology\hdl\gain_e.vhd
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE;
use IEEE.ELECTRICAL_SYSTEMS.all;

entity gain_e is
	generic (
		k: REAL := 1.0);  -- Gain multiplier
	port 	(	terminal input : electrical;
			terminal output: electrical);
end entity gain_e;

architecture simple of gain_e is

  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;

begin
	vout == k*vin;
end architecture simple;
--

-- C:\Mentor_Projects\CS2_Mixed_Technology\hdl\sum2_e.vhd
library IEEE;
library IEEE;
use IEEE.electrical_systems.all;
use IEEE.mechanical_systems.all;
use IEEE.fluidic_systems.all;
use IEEE.thermal_systems.all;
use IEEE.radiant_systems.all;

entity sum2_e is
	generic (k1, k2: real := 1.0);  -- Gain multipliers
	port 	(	terminal in1, in2: electrical;
			terminal output: electrical);
end entity sum2_e;

architecture simple of sum2_e is
  QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
  QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;

begin
	vout == k1*vin1 + k2*vin2;
end architecture simple;
--

-- C:\Mentor_Projects\CS2_Mixed_Technology\genhdl\rudder_z_domain\servo_z_diff.vhd
-- genhdl\rudder_z_domain/servo_z_diff.vhd
-- Generated by SystemVision netlister 1.0 build 2003.325.1
-- File created Sun Nov 23 09:32:09 2003

library ieee;
use ieee.std_logic_1164.all;
use ieee.electrical_systems.all;
use ieee.mechanical_systems.all;
use ieee.fluidic_systems.all;
use ieee.thermal_systems.all;
use ieee.radiant_systems.all;
library edulib;
use work.all;

entity SERVO_Z_DIFF is
   port( signal CLK : IN STD_LOGIC;
         terminal POS_FB :  ELECTRICAL;
         terminal SERVO_IN :  ELECTRICAL;
         terminal SERVO_OUT :  ELECTRICAL );
end entity SERVO_Z_DIFF;

architecture arch_SERVO_Z_DIFF of SERVO_Z_DIFF is
   terminal ERROR: ELECTRICAL;
   terminal SUMMER_FB: ELECTRICAL;
   terminal LL_IN: ELECTRICAL;
   terminal LIMIT_IN: ELECTRICAL;

   component SUM2_E
      generic( K1 : REAL:=1.0;
               K2 : REAL:=1.0 );
      port( terminal IN1 :  ELECTRICAL;
            terminal IN2 :  ELECTRICAL;
            terminal OUTPUT :  ELECTRICAL );
   end component SUM2_E;

   component LIMITER_2_E
      generic( LIMIT_HIGH : REAL:=4.8;
               LIMIT_LOW : REAL:=-4.8 );
      port( terminal INPUT :  ELECTRICAL;
            terminal OUTPUT :  ELECTRICAL );
   end component LIMITER_2_E;

   component LEAD_LAG_ZTF_DIFF
      generic( FP : REAL:=2000.0;
               FSMP : REAL:=10.0E3;
               FZ : REAL:=5.0;
               K : REAL:=400.0 );
      port( signal CLK : IN STD_LOGIC;
            terminal INPUT :  ELECTRICAL;
            terminal OUTPUT :  ELECTRICAL );
   end component LEAD_LAG_ZTF_DIFF;

   component GAIN_E
      generic( K : REAL:=1.0 );
      port( terminal INPUT :  ELECTRICAL;
            terminal OUTPUT :  ELECTRICAL );
   end component GAIN_E;

   for XCMP25: LEAD_LAG_ZTF_DIFF use entity WORK.LEAD_LAG_ZTF_DIFF;
   for LIM1: LIMITER_2_E use entity WORK.LIMITER_2_E;
   for FB_GAIN: GAIN_E use entity WORK.GAIN_E;
   for FORWARD_GAIN: GAIN_E use entity WORK.GAIN_E;
   for SUMMER: SUM2_E use entity WORK.SUM2_E;

begin

   XCMP25 : LEAD_LAG_ZTF_DIFF
      generic map ( FSMP => 10.0E3 )
      port map ( CLK => CLK,
                INPUT => LL_IN,
                OUTPUT => LIMIT_IN );

   LIM1 : LIMITER_2_E
      port map ( INPUT => LIMIT_IN,
                OUTPUT => SERVO_OUT );

   FB_GAIN : GAIN_E
      generic map ( K => -4.57 )
      port map ( INPUT => POS_FB,
                OUTPUT => SUMMER_FB );

   FORWARD_GAIN : GAIN_E
      generic map ( K => 100.0 )
      port map ( INPUT => ERROR,
                OUTPUT => LL_IN );

   SUMMER : SUM2_E
      port map ( IN1 => SERVO_IN,
                IN2 => SUMMER_FB,
                OUTPUT => ERROR );

end architecture arch_SERVO_Z_DIFF;

--

-- C:\Mentor_Projects\CS2_Mixed_Technology\hdl\servo_z_diff.vhd

library IEEE; use IEEE.std_logic_1164.all; use IEEE.math_real.all;
library IEEE; use IEEE.electrical_systems.all;

entity SERVO_Z_DIFF is
	generic (	k : real := 400.0;  -- Normalizing gain
				fwd_gain : real := 100.0;
				fb_gain : real := 4.57;
				lim_pos : real := 4.8;
				lim_neg : real := -4.8); 
	port 	(	signal clk : in std_logic; -- Clock is used for the Difference equations only
				terminal servo_in: electrical;
				terminal servo_out: electrical;
				terminal pos_fb: electrical);
end entity SERVO_Z_DIFF ;
-------------------------------------------------------------------------------
-- Transfer Function is derived from the following using the bilinear transform:
--
--              1 + (s/wz)
--  H(s) = K * ------------
--              1 + (s/wp)
-- 
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
-- Difference Equation:
--
--	Y(K) = k_diff*[AX(k) - BX(k-1) + CY(k-1)]
-------------------------------------------------------------------------------
architecture diff of SERVO_Z_DIFF is
  quantity vin across servo_in to ELECTRICAL_REF;
  quantity vout across iout through servo_out to ELECTRICAL_REF;
  quantity v_fb across pos_fb to electrical_ref;
  constant A : real := 0.6163507; -- current input coefficient
  constant B : real := 0.6144184; -- delayed input coefficient
  constant C : real := 0.2307692; -- delayed output coefficient
  
signal servo_out_z : real := 0.0;
begin
proc : process (clk)

	variable zi_dly1 : real := 0.0; -- Input delayed 1 clk cycle
	variable zo_dly1 : real := 0.0; -- Output delayed 1 clk cycle
	variable z_new : real := 0.0;	-- New output value this clk cycle
	variable error : real := 0.0;
	variable ll_in : real := 0.0;
	variable ll_out : real := 0.0;

 	begin  -- proc
 		-- Input summing junction module
 		error := vin - fb_gain*v_fb;
 		
 		-- Forward gain module
 		ll_in := fwd_gain*error;
 		
 		-- Lead-Lag filter module
		zo_dly1 := ll_out; -- Store previous output value
		z_new := A*ll_in - B*zi_dly1 + C*zo_dly1;
		zi_dly1 := ll_in; -- Store previous input value
		ll_out := z_new;
				
		-- Limiter module
		if ll_out/k > lim_pos then
			servo_out_z <= lim_pos;
		elsif ll_out/k < lim_neg then
			servo_out_z <= lim_neg;
		else servo_out_z <= k*ll_out;
		end if;
		
	end process;
	vout == servo_out_z'ramp(100.0e-9); -- Ensure continuous transitions on output
end diff;
--

-- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\Electrical/v_sine.vhd
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except 
-- compilations distributed in accordance with Section (d) of this license 
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such 
-- version is modified; (c) any modified version must include a conspicuous 
-- notice that this model has been modified and the date of modification; and 
-- (d) any compilations sold by you that include this model must include a 
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File       : v_sine.vhd
-- Author     : Mentor Graphics
-- Created    : 2001/06/16
-- Last update: 2003-05-13
-------------------------------------------------------------------------------
-- Description: Electrical sinusoidal voltage source
--              Includes frequency domain settings
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2001/06/16  1.0         Mentor Graphics     Created
-- 2001/07/03  1.1         Mentor Graphics     Changed generics from real to
--                                             voltage.
-------------------------------------------------------------------------------

library IEEE;
use IEEE.MATH_REAL.all;
-- Use IEEE natures and packages
use IEEE.ELECTRICAL_SYSTEMS.all;

entity v_sine is

  generic (
    freq      : real;                   -- frequency [Hertz]
    amplitude : voltage;                -- amplitude [Volts]
    phase     : real    := 0.0;         -- initial phase [Degrees]
    offset    : voltage := 0.0;         -- DC value [Volts]
    df        : real    := 0.0;         -- damping factor [1/second]
    ac_mag    : voltage := 1.0;         -- AC magnitude [Volts]
    ac_phase  : real    := 0.0);        -- AC phase [Degrees]

  port (
    terminal pos, neg : electrical);

end entity v_sine;

-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_sine is
-- Declare Branch Quantities
  quantity v across i through pos to neg;
-- Declare Quantity for Phase in radians (calculated below)
  quantity phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
  quantity ac_spec   : real spectrum ac_mag, math_2_pi*ac_phase/360.0;

begin
-- Convert phase to radians
  phase_rad == math_2_pi *(freq * NOW + phase / 360.0);

  if domain = quiescent_domain or domain = time_domain use
    v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
  else
    v == ac_spec;           -- used for Frequency (AC) analysis
  end use;

end architecture ideal;

-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--

-- C:\Mentor_Projects\CS2_Mixed_Technology\hdl\rudder.vhd
-------------------------------------------------------------------------------
-- Rudder Model (Rotational Spring)
--
--  Transfer Function:
--                            
--  torq =   -k*(theta - theta_0)
--
-- Where theta = input rotational angle,
-- torq = output rotational angle,
-- theta_0 = reference angle
-------------------------------------------------------------------------------

-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE;
use IEEE.mechanical_systems.all;

entity rudder is
  
  generic (
    k   : real := 1.0;            -- Spring constant
	theta_0 : real := 0.0);

  port (
    terminal rot    : rotational);   -- input rotational angle
     
end entity rudder;

architecture bhv of rudder is

  QUANTITY theta across torq through rot TO ROTATIONAL_REF;

  begin  -- bhv

   torq == k*(theta - theta_0);	-- Convert force to torque
   
end bhv;
--

-- C:\Mentor_Projects\CS2_Mixed_Technology\hdl\tran_linkage.vhd
library IEEE;
use IEEE.std_logic_arith.all;
library IEEE;
use IEEE.mechanical_systems.all;

entity tran_linkage is
port
(
      terminal p1, p2 : translational
);

begin

end tran_linkage;

architecture a1 of tran_linkage is

  QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
  QUANTITY pos_2 across frc_2 through p2 TO translational_ref;

begin

   pos_2 == pos_1;		-- Pass position 
   frc_2 == -frc_1;	-- Pass force

end;
--

-- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\Rotational/stop_r.vhd
-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except 
-- compilations distributed in accordance with Section (d) of this license 
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such 
-- version is modified; (c) any modified version must include a conspicuous 
-- notice that this model has been modified and the date of modification; and 
-- (d) any compilations sold by you that include this model must include a 
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File       : stop_r.vhd
-- Author     : Mentor Graphics
-- Created    : 2001/10/10
-- Last update: 2003-05-13
-------------------------------------------------------------------------------
-- Description: Mechanical Hard Stop (ROTATIONAL domain)
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2001/06/16  1.0         Mentor Graphics     Created
-- 2002/05/24  1.1         Mentor Graphics     Changed constants to type angle
-- 2003-04-02  1.2         Mentor Graphics     IEEE package update v1.3
-------------------------------------------------------------------------------

library IEEE;
use IEEE.MATH_REAL.all;
use IEEE.MECHANICAL_SYSTEMS.all;

entity stop_r is

  generic (
    k_stop    : stiffness;              -- Stiffness of hard stop [N/m]
    damp_stop : damping := 1.0e-9;      -- Damping of hard stop [N-sec/m]
    ang_max   : angle;                  -- Max angle [Radians]
    ang_min   : angle   := 0.0          -- Min angle [Radians]
    );

  port ( terminal ang1, ang2 : rotational);

end entity stop_r;

architecture ideal of stop_r is

  quantity velocity : velocity;
  quantity ang across trq through ang1 to ang2;

begin

  velocity == ang'dot;

  if ang'above(ang_max) use
    trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
  elsif ang'above(ang_min) use
    trq   == 0.0;
  else
    trq   == k_stop * (ang - ang_min) + (damp_stop * velocity);
  end use;

break on ang'above(ang_min), ang'above(ang_max);

end architecture ideal;

-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--

-- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\MixedTechnology/DCMotor_rv.vhd
-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except 
-- compilations distributed in accordance with Section (d) of this license 
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such 
-- version is modified; (c) any modified version must include a conspicuous 
-- notice that this model has been modified and the date of modification; and 
-- (d) any compilations sold by you that include this model must include a 
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File       : DCMotor_rv.vhd
-- Author     : Mentor Graphics
-- Created    : 2001/06/16
-- Last update: 2003-05-23
-------------------------------------------------------------------------------
-- Description: Basic DC Motor with output of type ROTATIONAL_VELOCITY
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2001/06/16  1.0         Mentor Graphics     Created    
-------------------------------------------------------------------------------

-- Use proposed IEEE natures and packages
library IEEE;
use IEEE.mechanical_systems.all;
use IEEE.electrical_systems.all;

entity DCMotor_rv is

  generic (
    r_wind : resistance;                -- Motor winding resistance [Ohm]
    kt     : real;                      -- Torque coefficient [N*m/Amp]
    l      : inductance;                -- Winding inductance [Henrys]
    d      : real;                      -- Damping coefficient [N*m/(rad/sec)]
    j      : moment_inertia);           -- Moment of inertia [kg*meter**2]

  port (terminal p1, p2 : electrical;
        terminal shaft_rotv : rotational_velocity);

end entity DCMotor_rv;

-------------------------------------------------------------------------------
-- Basic Architecture
-- Motor equations:  V = Kt*W + I*Rwind + L*dI/dt
--                   T = -Kt*I + D*W + J*dW/dt
-------------------------------------------------------------------------------
architecture basic of DCMotor_rv is

  quantity v across i through p1 to p2;
  quantity w across torq through shaft_rotv to rotational_velocity_ref;

begin

  torq == -1.0*kt*i + d*w + j*w'dot;
  v  == kt*w + i*r_wind + l*i'dot;

end architecture basic;

-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--

-- C:\Mentor_Projects\CS2_Mixed_Technology\hdl\horn_t2r.vhd
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
--  Transfer Function:
--                            
--  theta =   arcsin(pos/R) 
--
-- Where pos = input translational position,
-- R = horn radius, 
-- theta = output rotational angle
-------------------------------------------------------------------------------

-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE;
use IEEE.mechanical_systems.all;

entity horn_t2r is
  
  generic (
    R   : real := 1.0);            -- Rudder horn radius

  port (
    terminal pos    : translational;   -- input translational position port
    terminal theta   : rotational);  -- output angular position port
     
end entity horn_t2r ;

architecture bhv of horn_t2r is

  QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
  QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;

  begin  -- bhv
  if tran/R > 0.86 use
  	rot == 1.05;
  elsif tran/R < -0.86 use
  	rot == -1.05;
  else
   rot == arcsin(tran/R);	-- Convert translational to angle
  end use;
   rot_tq == -tran_frc*R;	-- Convert force to torque
   
end bhv;
--

-- C:\Mentor_Projects\CS2_Mixed_Technology\hdl\horn_r2t.vhd
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
--  Transfer Function:
--                            
--  tran =   R*sin(rot) 
--
-- Where pos = output translational position,
-- R = horn radius, 
-- theta = input rotational angle
-------------------------------------------------------------------------------

-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE;
use IEEE.mechanical_systems.all;

entity horn_r2t is
  
  generic (
    R   : real := 1.0);            		-- horn radius

  port (
    terminal theta    : ROTATIONAL;   	-- input angular position port
    terminal pos   : TRANSLATIONAL);  	-- output translational position port
     
end entity horn_r2t;

architecture bhv of horn_r2t is

  QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
  QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;

  begin			-- bhv
   tran == R*sin(rot);		-- Convert angle in to translational out
   tran_frc == -rot_tq/R;	-- Convert torque in to force out 
end bhv;
--

-- C:\Mentor_Projects\CS2_Mixed_Technology\genhdl\rudder_z_domain\rudder_z_domain.vhd
-- genhdl\rudder_z_domain/rudder_z_domain.vhd
-- Generated by SystemVision netlister 1.0 build 2003.325.1
-- File created Sun Nov 23 09:32:09 2003

library ieee;
use ieee.std_logic_1164.all;
use ieee.electrical_systems.all;
use ieee.mechanical_systems.all;
use ieee.fluidic_systems.all;
use ieee.thermal_systems.all;
use ieee.radiant_systems.all;
library edulib;
use work.all;

entity RUDDER_Z_DOMAIN is
end entity RUDDER_Z_DOMAIN;

architecture arch_RUDDER_Z_DOMAIN of RUDDER_Z_DOMAIN is
   terminal LINK_OUT: TRANSLATIONAL;
   terminal MOT_IN: ELECTRICAL;
   terminal FB_ROT2V: ELECTRICAL;
   terminal RUDDER_OUT: ROTATIONAL;
   terminal GEAR_IN: ROTATIONAL_VELOCITY;
   terminal CTL_HORN_IN: ROTATIONAL;
   terminal SRC_IN: ELECTRICAL;
   terminal LINK_IN: TRANSLATIONAL;
   signal CLK: STD_LOGIC;

   component HORN_R2T
      generic( R : REAL:=1.0 );
      port( terminal THETA :  ROTATIONAL;
            terminal POS :  TRANSLATIONAL );
   end component HORN_R2T;

   component HORN_T2R
      generic( R : REAL:=1.0 );
      port( terminal POS :  TRANSLATIONAL;
            terminal THETA :  ROTATIONAL );
   end component HORN_T2R;

   component TRAN_LINKAGE
      port( terminal P1 :  TRANSLATIONAL;
            terminal P2 :  TRANSLATIONAL );
   end component TRAN_LINKAGE;

   component GEAR_RV_R
      generic( RATIO : REAL:=1.0 );
      port( terminal ROTV1 :  ROTATIONAL_VELOCITY;
            terminal ROT2 :  ROTATIONAL );
   end component GEAR_RV_R;

   component ROT2V
      generic( K : REAL:=1.0 );
      port( terminal INPUT :  ROTATIONAL;
            terminal OUTPUT :  ELECTRICAL );
   end component ROT2V;

   component STOP_R
      generic( ANG_MAX : ANGLE;
               ANG_MIN : ANGLE:=0.0;
               DAMP_STOP : REAL:=1.0E-9;
               K_STOP : REAL );
      port( terminal ANG1 :  ROTATIONAL;
            terminal ANG2 :  ROTATIONAL );
   end component STOP_R;

   component SERVO_Z_DIFF
      port( signal CLK : IN STD_LOGIC;
            terminal POS_FB :  ELECTRICAL;
            terminal SERVO_IN :  ELECTRICAL;
            terminal SERVO_OUT :  ELECTRICAL );
   end component SERVO_Z_DIFF;

   component V_SINE
      generic( AC_MAG : VOLTAGE:=0.0;
               AC_PHASE : REAL:=0.0;
               AMPLITUDE : VOLTAGE;
               DF : REAL:=0.0;
               FREQ : REAL;
               OFFSET : VOLTAGE:=0.0;
               PHASE : REAL:=0.0 );
      port( terminal POS :  ELECTRICAL;
            terminal NEG :  ELECTRICAL );
   end component V_SINE;

   component CLOCK
      generic( PERIOD : TIME );
      port( signal CLK_OUT : OUT STD_LOGIC );
   end component CLOCK;

   component DCMOTOR_RV
      generic( D : REAL;
               J : MOMENT_INERTIA;
               KT : REAL;
               L : INDUCTANCE;
               R_WIND : RESISTANCE );
      port( terminal P1 :  ELECTRICAL;
            terminal P2 :  ELECTRICAL;
            terminal SHAFT_ROTV :  ROTATIONAL_VELOCITY );
   end component DCMOTOR_RV;

   component RUDDER
      generic( K : REAL:=1.0;
               THETA_0 : REAL:=0.0 );
      port( terminal ROT :  ROTATIONAL );
   end component RUDDER;

   for CLOCK1: CLOCK use entity WORK.CLOCK;
   for GAIN_FB: ROT2V use entity WORK.ROT2V;
   for GEAR1: GEAR_RV_R use entity WORK.GEAR_RV_R;
   for SERVO_Z_DIFF2: SERVO_Z_DIFF use entity WORK.SERVO_Z_DIFF(ARCH_SERVO_Z_DIFF);
   for V3: V_SINE use entity EDULIB.V_SINE;
   for RUDDER1: RUDDER use entity WORK.RUDDER;
   for LINKAGE1: TRAN_LINKAGE use entity WORK.TRAN_LINKAGE;
   for STOP1: STOP_R use entity EDULIB.STOP_R;
   for MOTOR1: DCMOTOR_RV use entity EDULIB.DCMOTOR_RV;
   for RUDDER_HORN: HORN_T2R use entity WORK.HORN_T2R;
   for GEAR_HORN: HORN_R2T use entity WORK.HORN_R2T;

begin

   CLOCK1 : CLOCK
      generic map ( PERIOD => 200.0 US )
      port map ( CLK_OUT => CLK );

   GAIN_FB : ROT2V
      generic map ( K => 1.0 )
      port map ( INPUT => CTL_HORN_IN,
                OUTPUT => FB_ROT2V );

   GEAR1 : GEAR_RV_R
      generic map ( RATIO => 0.01 )
      port map ( ROTV1 => GEAR_IN,
                ROT2 => CTL_HORN_IN );

   SERVO_Z_DIFF2 : SERVO_Z_DIFF
      port map ( CLK => CLK,
                POS_FB => FB_ROT2V,
                SERVO_IN => SRC_IN,
                SERVO_OUT => MOT_IN );

   V3 : V_SINE
      generic map ( AMPLITUDE => 4.7,
                    FREQ => 1.0 )
      port map ( POS => SRC_IN,
                NEG => ELECTRICAL_REF );

   RUDDER1 : RUDDER
      generic map ( K => 0.2 )
      port map ( ROT => RUDDER_OUT );

   LINKAGE1 : TRAN_LINKAGE
      port map ( P1 => LINK_IN,
                P2 => LINK_OUT );

   STOP1 : STOP_R
      generic map ( ANG_MAX => 1.05,
                    ANG_MIN => -1.05,
                    DAMP_STOP => 1.0E2,
                    K_STOP => 1.0E6 )
      port map ( ANG1 => CTL_HORN_IN,
                ANG2 => ROTATIONAL_REF );

   MOTOR1 : DCMOTOR_RV
      generic map ( D => 5.63E-6,
                    J => 168.0E-9,
                    KT => 3.43E-3,
                    L => 2.03E-3,
                    R_WIND => 2.2 )
      port map ( P1 => MOT_IN,
                P2 => ELECTRICAL_REF,
                SHAFT_ROTV => GEAR_IN );

   RUDDER_HORN : HORN_T2R
      port map ( POS => LINK_OUT,
                THETA => RUDDER_OUT );

   GEAR_HORN : HORN_R2T
      port map ( THETA => CTL_HORN_IN,
                POS => LINK_IN );

end architecture arch_RUDDER_Z_DOMAIN;

--