-- genhdl\tb_buckconverter_hier/buck_sw.vhd
-- Generated by SystemVision netlister 1.0 build 2003.310.1
-- File created Mon Nov 10 14:46:12 2003

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.electrical_systems.all;
USE ieee.mechanical_systems.all;
USE ieee.fluidic_systems.all;
USE ieee.thermal_systems.all;
USE ieee.radiant_systems.all;
LIBRARY edulib;
USE work.all;

entity BUCK_SW is
   port( terminal CTRL :  ELECTRICAL;
         terminal INPUT :  ELECTRICAL;
         terminal OUTPUT :  ELECTRICAL;
         terminal REF :  ELECTRICAL );
end entity BUCK_SW;

architecture arch_BUCK_SW of BUCK_SW is
   terminal VSAW: ELECTRICAL;
   signal COMP_OUT: STD_LOGIC;
   signal SW_CTRL: STD_LOGIC;

   component INVERTER
      generic( DELAY : TIME:=0 NS );
      port( signal INPUT : IN STD_LOGIC;
            signal OUTPUT : OUT STD_LOGIC );
   end component INVERTER;

   component V_PULSE
      generic( AC_MAG : VOLTAGE:=1.0;
               AC_PHASE : REAL:=0.0;
               DELAY : TIME:=0 MS;
               INITIAL : VOLTAGE:=0.0;
               PERIOD : TIME;
               PULSE : VOLTAGE;
               TI2P : TIME:=1 NS;
               TP2I : TIME:=1 NS;
               WIDTH : TIME );
      port( terminal POS :  ELECTRICAL;
            terminal NEG :  ELECTRICAL );
   end component V_PULSE;

   component DIODE
      generic( ISAT : CURRENT:=1.0E-14 );
      port( terminal P :  ELECTRICAL;
            terminal N :  ELECTRICAL );
   end component DIODE;

   component SWITCH_DIG
      generic( R_CLOSED : RESISTANCE:=0.001;
               R_OPEN : RESISTANCE:=1.0E6;
               TRANS_TIME : REAL:=1.0E-9 );
      port( signal SW_STATE : IN STD_LOGIC;
            terminal P1 :  ELECTRICAL;
            terminal P2 :  ELECTRICAL );
   end component SWITCH_DIG;

   component COMPARATOR_D
      port( terminal IN_POS :  ELECTRICAL;
            terminal IN_NEG :  ELECTRICAL;
            signal OUTPUT : OUT STD_LOGIC := '1' );
   end component COMPARATOR_D;

   for INVERTER1: INVERTER use entity EDULIB.INVERTER;
   for V_PULSE1: V_PULSE use entity EDULIB.V_PULSE;
   for COMPARATOR1: COMPARATOR_D use entity EDULIB.COMPARATOR_D;
   for SW1: SWITCH_DIG use entity EDULIB.SWITCH_DIG;
   for D1: DIODE use entity EDULIB.DIODE(IDEAL);

begin

   INVERTER1 : INVERTER
      port map ( INPUT => COMP_OUT,
                OUTPUT => SW_CTRL );

   V_PULSE1 : V_PULSE
      generic map ( DELAY => 10US,
                    PERIOD => 40.001US,
                    PULSE => 2.5,
                    TI2P => 40US,
                    TP2I => 0.1NS,
                    WIDTH => 0.1NS )
      port map ( POS => VSAW,
                NEG => ELECTRICAL_REF );

   COMPARATOR1 : COMPARATOR_D
      port map ( IN_POS => VSAW,
                IN_NEG => CTRL,
                OUTPUT => COMP_OUT );

   SW1 : SWITCH_DIG
      port map ( SW_STATE => SW_CTRL,
                P1 => INPUT,
                P2 => OUTPUT );

   D1 : DIODE
      port map ( P => REF,
                N => OUTPUT );

end architecture arch_BUCK_SW;