-- genhdl\cs3_buckconverter/cs3_buckconverter.vhd
-- Generated by SystemVision netlister 1.0 build 2003.310.1
-- File created Mon Nov 10 14:39:22 2003

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.electrical_systems.all;
USE ieee.mechanical_systems.all;
USE ieee.fluidic_systems.all;
USE ieee.thermal_systems.all;
USE ieee.radiant_systems.all;
LIBRARY edulib;
USE work.all;

entity CS3_BUCKCONVERTER is
end entity CS3_BUCKCONVERTER;

architecture arch_CS3_BUCKCONVERTER of CS3_BUCKCONVERTER is
   terminal VCTRL_INIT: ELECTRICAL;
   terminal VMID: ELECTRICAL;
   terminal VIN: ELECTRICAL;
   terminal VOUT: ELECTRICAL;
   terminal VCTRL: ELECTRICAL;
   terminal VREF: ELECTRICAL;
   terminal VCOMP_OUT: ELECTRICAL;

   component V_PULSE
      generic( AC_MAG : VOLTAGE:=0.0;
               AC_PHASE : REAL:=0.0;
               DELAY : TIME:=0 MS;
               INITIAL : VOLTAGE:=0.0;
               PERIOD : TIME;
               PULSE : VOLTAGE;
               TI2P : TIME:=1 NS;
               TP2I : TIME:=1 NS;
               WIDTH : TIME );
      port( terminal POS :  ELECTRICAL;
            terminal NEG :  ELECTRICAL );
   end component V_PULSE;

   component SW_LOOPCTRL
      generic( R_CLOSED : RESISTANCE:=1.0E-3;
               R_OPEN : RESISTANCE:=1.0E6;
               SW_STATE : INTEGER:=1 );
      port( terminal C :  ELECTRICAL;
            terminal P1 :  ELECTRICAL;
            terminal P2 :  ELECTRICAL );
   end component SW_LOOPCTRL;

   component INDUCTOR
      generic( IND : INDUCTANCE;
               I_IC : REAL:=REAL'LOW );
      port( terminal P1 :  ELECTRICAL;
            terminal P2 :  ELECTRICAL );
   end component INDUCTOR;

   component V_CONSTANT
      generic( AC_MAG : VOLTAGE:=0.0;
               AC_PHASE : REAL:=0.0;
               LEVEL : VOLTAGE );
      port( terminal POS :  ELECTRICAL;
            terminal NEG :  ELECTRICAL );
   end component V_CONSTANT;

   component PWL_LOAD
      generic( LOAD_ENABLE : STRING:="YES";
               RES1 : RESISTANCE;
               RES2 : RESISTANCE;
               RES_INIT : RESISTANCE;
               T1 : TIME;
               T2 : TIME );
      port( terminal P1 :  ELECTRICAL;
            terminal P2 :  ELECTRICAL );
   end component PWL_LOAD;

   component COMP_2P2Z
      generic( FP1 : REAL:=7.5E3;
               FP2 : REAL:=531.0E3;
               FZ1 : REAL:=806.0;
               FZ2 : REAL:=806.0;
               GAIN : REAL:=100.0 );
      port( terminal INPUT :  ELECTRICAL;
            terminal OUTPUT :  ELECTRICAL;
            terminal REF :  ELECTRICAL );
   end component COMP_2P2Z;

   component CAPACITOR
      generic( CAP : CAPACITANCE;
               R_ESR : RESISTANCE:=0.0;
               V_IC : REAL:=REAL'LOW );
      port( terminal P1 :  ELECTRICAL;
            terminal P2 :  ELECTRICAL );
   end component CAPACITOR;

   component BUCK_AVG
      generic( VD : VOLTAGE:=0.7;
               VRAMP : VOLTAGE:=2.5 );
      port( terminal INPUT :  ELECTRICAL;
            terminal OUTPUT :  ELECTRICAL;
            terminal REF :  ELECTRICAL;
            terminal CTRL :  ELECTRICAL );
   end component BUCK_AVG;

   for COMP_2P2Z4: COMP_2P2Z use entity WORK.COMP_2P2Z;
   for V_PULSE1: V_PULSE use entity EDULIB.V_PULSE;
   for BUCK_AVG1: BUCK_AVG use entity WORK.BUCK_AVG(SIMPLE);
   for ELECTRICAL_LOAD6: PWL_LOAD use entity WORK.PWL_LOAD;
   for SW2: SW_LOOPCTRL use entity WORK.SW_LOOPCTRL;
   for V_DC2: V_CONSTANT use entity EDULIB.V_CONSTANT(IDEAL);
   for V_DC1: V_CONSTANT use entity EDULIB.V_CONSTANT;
   for C1: CAPACITOR use entity WORK.CAPACITOR(ESR);
   for L1: INDUCTOR use entity EDULIB.INDUCTOR(IDEAL);

begin

   COMP_2P2Z4 : COMP_2P2Z
      generic map ( FZ1 => 403.0,
                    FZ2 => 403.0,
                    GAIN => 100.0 )
      port map ( INPUT => VOUT,
                OUTPUT => VCOMP_OUT,
                REF => VREF );

   V_PULSE1 : V_PULSE
      generic map ( DELAY => 50 MS,
                    INITIAL => 42.0,
                    PERIOD => 1000MS,
                    PULSE => 30.0,
                    WIDTH => 100MS )
      port map ( POS => VIN,
                NEG => ELECTRICAL_REF );

   BUCK_AVG1 : BUCK_AVG
      port map ( INPUT => VIN,
                OUTPUT => VMID,
                REF => ELECTRICAL_REF,
                CTRL => VCTRL );

   ELECTRICAL_LOAD6 : PWL_LOAD
      generic map ( LOAD_ENABLE => "YES",
                    RES1 => 1.0,
                    RES2 => 5.0,
                    RES_INIT => 2.4,
                    T1 => 5MS,
                    T2 => 30 MS )
      port map ( P1 => VOUT,
                P2 => ELECTRICAL_REF );

   SW2 : SW_LOOPCTRL
      generic map ( SW_STATE => 1 )
      port map ( C => VCTRL,
                P1 => VCOMP_OUT,
                P2 => VCTRL_INIT );

   V_DC2 : V_CONSTANT
      generic map ( LEVEL => 4.8 )
      port map ( POS => VREF,
                NEG => ELECTRICAL_REF );

   V_DC1 : V_CONSTANT
      generic map ( AC_MAG => 1.0,
                    LEVEL => 0.327 )
      port map ( POS => VCTRL_INIT,
                NEG => ELECTRICAL_REF );

   C1 : CAPACITOR
      generic map ( CAP => 6.0E-6,
                    R_ESR => 50.0E-3,
                    V_IC => 4.8 )
      port map ( P1 => VOUT,
                P2 => ELECTRICAL_REF );

   L1 : INDUCTOR
      generic map ( IND => 6.5E-3 )
      port map ( P1 => VMID,
                P2 => VOUT );

end architecture arch_CS3_BUCKCONVERTER;