library IEEE;
use IEEE.electrical_systems.all;

entity pwl_load is
  generic (
    load_enable: string := "yes";
    res_init : resistance;
    res1 : resistance;                  
    t1 : time;
    res2 : resistance;
    t2 : time);
  port (terminal p1, p2 : electrical);
end entity pwl_load;

architecture ideal of pwl_load is
  quantity v across i through p1 to p2;
  signal res_signal : resistance := res_init;
begin

  if load_enable = "YES" use
    if domain = quiescent_domain or domain = frequency_domain use
       v == i*res_init; 
    else 
	   v == i*res_signal'ramp(1.0e-6, 1.0e-6);
	end use;
  else 
    i == 0.0;
  end use;

 -- purpose: Create Events to change resistance at specified times
 -- type   : combinational
 -- inputs :
 -- outputs: res
CreateEvent: process is
 begin  -- process CreateEvent
   wait for t1;
   res_signal <= res1;
   wait for (t2-t1);
   res_signal <= res2;
   wait;
 end process CreateEvent; 

end architecture ideal;