-- genhdl\tb_buckconverter/tb_buckconverter.vhd
-- Generated by SystemVision netlister 1.0 build 2003.310.1
-- File created Mon Nov 10 14:48:32 2003

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.electrical_systems.all;
USE ieee.mechanical_systems.all;
USE ieee.fluidic_systems.all;
USE ieee.thermal_systems.all;
USE ieee.radiant_systems.all;
LIBRARY edulib;
USE work.all;

entity TB_BUCKCONVERTER is
end entity TB_BUCKCONVERTER;

architecture arch_TB_BUCKCONVERTER of TB_BUCKCONVERTER is
   terminal VMID: ELECTRICAL;
   terminal VIN: ELECTRICAL;
   terminal VOUT: ELECTRICAL;
   signal CTRL: STD_LOGIC;

   component DIODE
      generic( ISAT : CURRENT:=1.0E-14 );
      port( terminal P :  ELECTRICAL;
            terminal N :  ELECTRICAL );
   end component DIODE;

   component INDUCTOR
      generic( IND : INDUCTANCE;
               I_IC : REAL:=REAL'LOW );
      port( terminal P1 :  ELECTRICAL;
            terminal P2 :  ELECTRICAL );
   end component INDUCTOR;

   component V_CONSTANT
      generic( AC_MAG : VOLTAGE:=0.0;
               AC_PHASE : REAL:=0.0;
               LEVEL : VOLTAGE );
      port( terminal POS :  ELECTRICAL;
            terminal NEG :  ELECTRICAL );
   end component V_CONSTANT;

   component RESISTOR
      generic( RES : RESISTANCE );
      port( terminal P1 :  ELECTRICAL;
            terminal P2 :  ELECTRICAL );
   end component RESISTOR;

   component CLOCK_FREQ
      generic( DUTY : REAL:=0.5;
               FREQ : REAL );
      port( signal CLK_OUT : OUT STD_LOGIC );
   end component CLOCK_FREQ;

   component SWITCH_DIG
      generic( R_CLOSED : RESISTANCE:=0.001;
               R_OPEN : RESISTANCE:=1.0E6;
               TRANS_TIME : REAL:=1.0E-9 );
      port( signal SW_STATE : IN STD_LOGIC;
            terminal P1 :  ELECTRICAL;
            terminal P2 :  ELECTRICAL );
   end component SWITCH_DIG;

   component CAPACITOR
      generic( CAP : CAPACITANCE;
               V_IC : REAL:=REAL'LOW );
      port( terminal P1 :  ELECTRICAL;
            terminal P2 :  ELECTRICAL );
   end component CAPACITOR;

   for SW1: SWITCH_DIG use entity EDULIB.SWITCH_DIG;
   for D1: DIODE use entity EDULIB.DIODE(IDEAL);
   for CLOCK_FREQ1: CLOCK_FREQ use entity EDULIB.CLOCK_FREQ(IDEAL);
   for RLOAD: RESISTOR use entity EDULIB.RESISTOR(IDEAL);
   for VINDC: V_CONSTANT use entity EDULIB.V_CONSTANT;
   for C1: CAPACITOR use entity EDULIB.CAPACITOR(IDEAL);
   for L1: INDUCTOR use entity EDULIB.INDUCTOR(IDEAL);

begin

   SW1 : SWITCH_DIG
      port map ( SW_STATE => CTRL,
                P1 => VIN,
                P2 => VMID );

   D1 : DIODE
      port map ( P => ELECTRICAL_REF,
                N => VMID );

   CLOCK_FREQ1 : CLOCK_FREQ
      generic map ( DUTY => 0.131,
                    FREQ => 25.0E3 )
      port map ( CLK_OUT => CTRL );

   RLOAD : RESISTOR
      generic map ( RES => 2.4 )
      port map ( P1 => VOUT,
                P2 => ELECTRICAL_REF );

   VINDC : V_CONSTANT
      generic map ( LEVEL => 42.0 )
      port map ( POS => VIN,
                NEG => ELECTRICAL_REF );

   C1 : CAPACITOR
      generic map ( CAP => 1.5E-6 )
      port map ( P1 => VOUT,
                P2 => ELECTRICAL_REF );

   L1 : INDUCTOR
      generic map ( IND => 6.5E-3 )
      port map ( P1 => VMID,
                P2 => VOUT );

end architecture arch_TB_BUCKCONVERTER;