-- genhdl\tb_buckconverter_hier/tb_buckconverter_hier.vhd
-- Generated by SystemVision netlister 1.0 build 2003.310.1
-- File created Mon Nov 10 14:46:12 2003

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.electrical_systems.all;
USE ieee.mechanical_systems.all;
USE ieee.fluidic_systems.all;
USE ieee.thermal_systems.all;
USE ieee.radiant_systems.all;
LIBRARY edulib;
USE work.all;

entity TB_BUCKCONVERTER_HIER is
end entity TB_BUCKCONVERTER_HIER;

architecture arch_TB_BUCKCONVERTER_HIER of TB_BUCKCONVERTER_HIER is
   terminal VMID: ELECTRICAL;
   terminal VIN: ELECTRICAL;
   terminal VOUT: ELECTRICAL;
   terminal VCTRL: ELECTRICAL;

   component BUCK_SW
      port( terminal CTRL :  ELECTRICAL;
            terminal INPUT :  ELECTRICAL;
            terminal OUTPUT :  ELECTRICAL;
            terminal REF :  ELECTRICAL );
   end component BUCK_SW;

   component INDUCTOR
      generic( IND : INDUCTANCE;
               I_IC : REAL:=REAL'LOW );
      port( terminal P1 :  ELECTRICAL;
            terminal P2 :  ELECTRICAL );
   end component INDUCTOR;

   component V_CONSTANT
      generic( AC_MAG : VOLTAGE:=0.0;
               AC_PHASE : REAL:=0.0;
               LEVEL : VOLTAGE );
      port( terminal POS :  ELECTRICAL;
            terminal NEG :  ELECTRICAL );
   end component V_CONSTANT;

   component RESISTOR
      generic( RES : RESISTANCE );
      port( terminal P1 :  ELECTRICAL;
            terminal P2 :  ELECTRICAL );
   end component RESISTOR;

   component CAPACITOR
      generic( CAP : CAPACITANCE;
               R_ESR : RESISTANCE:=0.0;
               V_IC : REAL:=REAL'LOW );
      port( terminal P1 :  ELECTRICAL;
            terminal P2 :  ELECTRICAL );
   end component CAPACITOR;

   for V_DC2: V_CONSTANT use entity EDULIB.V_CONSTANT;
   for V_DC1: V_CONSTANT use entity EDULIB.V_CONSTANT;
   for BUCK_SW2: BUCK_SW use entity WORK.BUCK_SW(ARCH_BUCK_SW);
   for ROUT: RESISTOR use entity EDULIB.RESISTOR(IDEAL);
   for C1: CAPACITOR use entity WORK.CAPACITOR(ESR);
   for L1: INDUCTOR use entity EDULIB.INDUCTOR(IDEAL);

begin

   V_DC2 : V_CONSTANT
      generic map ( LEVEL => 42.0 )
      port map ( POS => VIN,
                NEG => ELECTRICAL_REF );

   V_DC1 : V_CONSTANT
      generic map ( LEVEL => 0.327 )
      port map ( POS => VCTRL,
                NEG => ELECTRICAL_REF );

   BUCK_SW2 : BUCK_SW
      port map ( CTRL => VCTRL,
                INPUT => VIN,
                OUTPUT => VMID,
                REF => ELECTRICAL_REF );

   ROUT : RESISTOR
      generic map ( RES => 2.4 )
      port map ( P1 => VOUT,
                P2 => ELECTRICAL_REF );

   C1 : CAPACITOR
      generic map ( CAP => 1.5E-6,
                    R_ESR => 50.0E-3 )
      port map ( P1 => VOUT,
                P2 => ELECTRICAL_REF );

   L1 : INDUCTOR
      generic map ( IND => 6.5E-3,
                    I_IC => 0.0 )
      port map ( P1 => VMID,
                P2 => VOUT );

end architecture arch_TB_BUCKCONVERTER_HIER;