-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation 
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
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-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
-- license to use, reproduce, modify and distribute this model, provided that:
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-- compilations distributed in accordance with Section (d) of this license 
-- agreement; (b) the comment text embedded in this model is included verbatim
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-- notice that this model has been modified and the date of modification; and 
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--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
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-------------------------------------------------------------------------------
-- File       : data_time_vector.vhd
-- Author     : Mentor Graphics
-- Created    : 2003-05-30
-- Last update: 
-------------------------------------------------------------------------------
-- Description: Digital Data Source. Data pattern is controlled by a time_vector
--              of specified switching times. Pattern repeats (wraps) after completion. 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version     Author              Description
-- 2003-05-30  1.0         Mentor Graphics     Created
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
Library MGC_AMS; 
use MGC_AMS.Conversion.all; 

entity data_time_vector is
	generic (s0    : std_logic := '0';  -- Initial data value
			 t0    : time := 100 ps;    -- Initial value hold time ... not part of repetition
			 tdata : time_vector);	    -- Sequence of logic switching times 
	port 	(d_output : out std_logic);
end entity data_time_vector;


architecture behavioral of data_time_vector is
begin

CreateSequence: process
variable i : integer := 0;
variable out_state : std_logic;
begin
	out_state := s0;
	d_output <= out_state;
	wait until domain = time_domain;
	wait for t0;
  	periodic: loop
	i := 0;
    	for i in tdata'range loop
			out_state := not out_state;
      		d_output <= out_state;
      		wait for tdata(i);
		end loop;
    end loop periodic;
end process CreateSequence;

end architecture behavioral;

-------------------------------------------------------------------------------
-- Copyright (c) 2003 Mentor Graphics Corporation
-------------------------------------------------------------------------------