-- genhdl\tb_bfsk/tb_bfsk.vhd
-- Generated by SystemVision netlister 1.0 build 2003.310.1
-- File created Mon Nov 10 17:17:34 2003

library edulib;
library ieee;
library mgc_ams;
use ieee.electrical_systems.all;
use ieee.fluidic_systems.all;
use ieee.mechanical_systems.all;
use ieee.radiant_systems.all;
use ieee.std_logic_1164.all;
use ieee.thermal_systems.all;
use mgc_ams.conversion.all;
use work.all;

entity TB_BFSK is
end entity TB_BFSK;

architecture arch_TB_BFSK of TB_BFSK is
   terminal BFSK_OUT: ELECTRICAL;
   signal BITSTREAM: STD_LOGIC;
   signal F_BFSK_OUT: REAL:=0.0;

   component DATA_TIME_VECTOR
      generic( S0 : STD_LOGIC:='0';
               T0 : TIME:=100 PS;
               TDATA : TIME_VECTOR );
      port( signal D_OUTPUT : OUT STD_LOGIC );
   end component DATA_TIME_VECTOR;

   component BFSK
      generic( AMP : VOLTAGE:=1.0;
               DELTA_F : REAL:=5.0E3;
               FC : REAL:=455.0E3;
               OFFSET : VOLTAGE:=0.0 );
      port( signal D_IN : IN STD_LOGIC;
            terminal A_OUT :  ELECTRICAL );
   end component BFSK;

   component MEASFREQ
      generic( THRES : REAL:=0.0 );
      port( terminal INPUT :  ELECTRICAL;
            signal F_OUT : OUT REAL:=0.0 );
   end component MEASFREQ;

   for BFSK3: BFSK use entity WORK.BFSK;
   for DATA1: DATA_TIME_VECTOR use entity WORK.DATA_TIME_VECTOR(BEHAVIORAL);
   for MEASFREQ1: MEASFREQ use entity EDULIB.MEASFREQ;

begin

   BFSK3 : BFSK
      port map ( D_IN => BITSTREAM,
                A_OUT => BFSK_OUT );

   DATA1 : DATA_TIME_VECTOR
      generic map ( T0 => 50 US,
                    TDATA => (50US,50US,50US,100US,200US,50US,50US,10MS) )
      port map ( D_OUTPUT => BITSTREAM );

   MEASFREQ1 : MEASFREQ
      port map ( INPUT => BFSK_OUT,
                F_OUT => F_BFSK_OUT );

end architecture arch_TB_BFSK;