-- genhdl\tb_commsys_pll/tb_commsys_pll.vhd
-- Generated by SystemVision netlister 1.0 build 2003.310.1
-- File created Mon Nov 10 17:23:01 2003

library edulib;
library ieee;
library mgc_ams;
use ieee.electrical_systems.all;
use ieee.fluidic_systems.all;
use ieee.mechanical_systems.all;
use ieee.radiant_systems.all;
use ieee.std_logic_1164.all;
use ieee.thermal_systems.all;
use mgc_ams.conversion.all;
use work.all;

entity TB_COMMSYS_PLL is
end entity TB_COMMSYS_PLL;

architecture arch_TB_COMMSYS_PLL of TB_COMMSYS_PLL is
   terminal BFSK_OUT: ELECTRICAL;
   signal BITSTREAM: STD_LOGIC;
   signal F_BFSK_OUT: REAL:=0.0;
   terminal VCO_OUT: ELECTRICAL;
   terminal LF_PLL_OUT: ELECTRICAL;
   terminal LPF_OUT: ELECTRICAL;
   signal BASEBAND: STD_LOGIC;
   signal F_VCO_OUT: REAL:=0.0;

   component E_LPF_2ND
      generic( FP : REAL:=100.0;
               FSMP : REAL:=10.0E3;
               K : REAL:=1.0;
               Q : REAL:=0.707 );
      port( terminal INPUT :  ELECTRICAL;
            terminal OUTPUT :  ELECTRICAL );
   end component E_LPF_2ND;

   component DATA_TIME_VECTOR
      generic( S0 : STD_LOGIC:='0';
               T0 : TIME:=100 PS;
               TDATA : TIME_VECTOR );
      port( signal D_OUTPUT : OUT STD_LOGIC );
   end component DATA_TIME_VECTOR;

   component A2D_BIT
      generic( THRES : REAL:=2.5 );
      port( terminal A :  ELECTRICAL;
            signal D : OUT STD_LOGIC );
   end component A2D_BIT;

   component PLL
      generic( FP : REAL:=20.0E3;
               FV : REAL:=1.0E6;
               FZ : REAL:=1.0E6;
               KV : REAL:=100.0E3 );
      port( terminal INPUT :  ELECTRICAL;
            terminal LF_OUT :  ELECTRICAL;
            terminal VCO_OUT :  ELECTRICAL );
   end component PLL;

   component BFSK
      generic( AMP : VOLTAGE:=1.0;
               DELTA_F : REAL:=5.0E3;
               FC : REAL:=455.0E3;
               OFFSET : VOLTAGE:=0.0 );
      port( signal D_IN : IN STD_LOGIC;
            terminal A_OUT :  ELECTRICAL );
   end component BFSK;

   component MEASFREQ
      generic( THRES : REAL:=0.0 );
      port( terminal INPUT :  ELECTRICAL;
            signal F_OUT : OUT REAL:=0.0 );
   end component MEASFREQ;

   for A2D1: A2D_BIT use entity EDULIB.A2D_BIT;
   for DATA1: DATA_TIME_VECTOR use entity WORK.DATA_TIME_VECTOR(BEHAVIORAL);
   for MEASFREQ1: MEASFREQ use entity EDULIB.MEASFREQ;
   for MEASFREQ2: MEASFREQ use entity EDULIB.MEASFREQ;
   for E_LPF_2ND1: E_LPF_2ND use entity EDULIB.E_LPF_2ND(S_DMN);
   for BFSK4: BFSK use entity WORK.BFSK;
   for PLL3: PLL use entity WORK.PLL;

begin

   A2D1 : A2D_BIT
      port map ( A => LPF_OUT,
                D => BASEBAND );

   DATA1 : DATA_TIME_VECTOR
      generic map ( T0 => 50 US,
                    TDATA => (50US,50US,50US,100US,200US,50US,50US,10MS) )
      port map ( D_OUTPUT => BITSTREAM );

   MEASFREQ1 : MEASFREQ
      port map ( INPUT => BFSK_OUT,
                F_OUT => F_BFSK_OUT );

   MEASFREQ2 : MEASFREQ
      port map ( INPUT => VCO_OUT,
                F_OUT => F_VCO_OUT );

   E_LPF_2ND1 : E_LPF_2ND
      generic map ( FP => 50.0E3,
                    K => 200.0 )
      port map ( INPUT => LF_PLL_OUT,
                OUTPUT => LPF_OUT );

   BFSK4 : BFSK
      port map ( D_IN => BITSTREAM,
                A_OUT => BFSK_OUT );

   PLL3 : PLL
      generic map ( FV => 455.0E3,
                    FZ => 500.0E3,
                    KV => 100.0E3 )
      port map ( INPUT => BFSK_OUT,
                LF_OUT => LF_PLL_OUT,
                VCO_OUT => VCO_OUT );

end architecture arch_TB_COMMSYS_PLL;