-- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\lead_lag_e.vhd ------------------------------------------------------------------------------- -- Lead-Lag Filter -- -- Transfer Function: -- -- (s + w1) -- H(s) = k * ---------- -- (s + w2) -- -- DC Gain = k*w1/w2 ------------------------------------------------------------------------------- library IEEE; use IEEE.electrical_systems.all; use ieee.math_real.all; entity lead_lag_e is generic ( k: real := 1.0; -- Gain multiplier f1: real := 10.0; -- First break frequency (zero) f2: real := 100.0); -- Second break frequency (pole) port ( terminal input: electrical; terminal output: electrical); end entity lead_lag_e; architecture simple of lead_lag_e is QUANTITY vin ACROSS input TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; quantity vin_temp : real; constant w1 : real := f1*math_2_pi; constant w2 : real := f2*math_2_pi; constant num : real_vector := (w1, 1.0); constant den : real_vector := (w2, 1.0); begin vin_temp == vin; vout == k*vin_temp'ltf(num, den); end architecture simple; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\limiter_2_e.vhd library IEEE; use IEEE.electrical_systems.all; library IEEE; use ieee.math_real.all; entity limiter_2_e is generic ( limit_high : real := 4.8; -- upper limit limit_low : real := -4.8); -- lower limit port ( terminal input: electrical; terminal output: electrical); end entity limiter_2_e; architecture simple of limiter_2_e is QUANTITY vin ACROSS input TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; constant slope : real := 1.0e-4; begin if vin > limit_high use -- Upper limit exceeded, so limit input signal vout == limit_high + slope*(vin - limit_high); elsif vin < limit_low use -- Lower limit exceeded, so limit input signal vout == limit_low + slope*(vin - limit_low); else -- No limit exceeded, so pass input signal as is vout == vin; end use; break on vin'above(limit_high), vin'above(limit_low); end architecture simple; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\gain_e.vhd library IEEE; use IEEE.MATH_REAL.all; use IEEE.ELECTRICAL_SYSTEMS.all; entity gain_e is generic ( k: REAL := 1.0); -- Gain multiplier port ( terminal input : electrical; terminal output: electrical); end entity gain_e; architecture simple of gain_e is QUANTITY vin ACROSS input TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; begin vout == k*vin; end architecture simple; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\sum2_e.vhd library IEEE; library IEEE; use IEEE.electrical_systems.all; use IEEE.mechanical_systems.all; use IEEE.fluidic_systems.all; use IEEE.thermal_systems.all; use IEEE.radiant_systems.all; entity sum2_e is generic (k1, k2: real := 1.0); -- Gain multipliers port ( terminal in1, in2: electrical; terminal output: electrical); end entity sum2_e; architecture simple of sum2_e is QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF; QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; begin vout == k1*vin1 + k2*vin2; end architecture simple; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\genhdl\airplane_hcl\rudder_servo.vhd -- genhdl\airplane_hcl/rudder_servo.vhd -- Generated by SystemVision netlister 1.0 build 2003.325.1 -- File created Sat Nov 22 14:06:19 2003 library edulib; library ieee; library mgc_ams; use ieee.electrical_systems.all; use ieee.fluidic_systems.all; use ieee.mechanical_systems.all; use ieee.radiant_systems.all; use ieee.std_logic_1164.all; use ieee.thermal_systems.all; use mgc_ams.conversion.all; use work.all; entity RUDDER_SERVO is port( terminal POS_FB : ELECTRICAL; terminal SERVO_IN : ELECTRICAL; terminal SERVO_OUT : ELECTRICAL ); end entity RUDDER_SERVO; architecture arch_RUDDER_SERVO of RUDDER_SERVO is terminal LL_OUT: ELECTRICAL; terminal ERROR: ELECTRICAL; terminal SUMMER_FB: ELECTRICAL; terminal LL_IN: ELECTRICAL; component SUM2_E generic( K1 : REAL:=1.0; K2 : REAL:=1.0 ); port( terminal IN1 : ELECTRICAL; terminal IN2 : ELECTRICAL; terminal OUTPUT : ELECTRICAL ); end component SUM2_E; component LEAD_LAG_E generic( F1 : REAL:=10.0; F2 : REAL:=100.0; K : REAL:=1.0 ); port( terminal INPUT : ELECTRICAL; terminal OUTPUT : ELECTRICAL ); end component LEAD_LAG_E; component LIMITER_2_E generic( LIMIT_HIGH : REAL:=4.8; LIMIT_LOW : REAL:=-4.8 ); port( terminal INPUT : ELECTRICAL; terminal OUTPUT : ELECTRICAL ); end component LIMITER_2_E; component GAIN_E generic( K : REAL:=1.0 ); port( terminal INPUT : ELECTRICAL; terminal OUTPUT : ELECTRICAL ); end component GAIN_E; for LEAD_LAG: LEAD_LAG_E use entity WORK.LEAD_LAG_E; for SERVO_LIMITER: LIMITER_2_E use entity WORK.LIMITER_2_E; for FB_GAIN: GAIN_E use entity WORK.GAIN_E; for FORWARD_GAIN: GAIN_E use entity WORK.GAIN_E; for SUMMER: SUM2_E use entity WORK.SUM2_E; begin LEAD_LAG : LEAD_LAG_E generic map ( F1 => 5.0, F2 => 2000.0, K => 400.0 ) port map ( INPUT => LL_IN, OUTPUT => LL_OUT ); SERVO_LIMITER : LIMITER_2_E generic map ( LIMIT_HIGH => 4.8, LIMIT_LOW => -4.8 ) port map ( INPUT => LL_OUT, OUTPUT => SERVO_OUT ); FB_GAIN : GAIN_E generic map ( K => -4.57 ) port map ( INPUT => POS_FB, OUTPUT => SUMMER_FB ); FORWARD_GAIN : GAIN_E generic map ( K => 100.0 ) port map ( INPUT => ERROR, OUTPUT => LL_IN ); SUMMER : SUM2_E port map ( IN1 => SERVO_IN, IN2 => SUMMER_FB, OUTPUT => ERROR ); end architecture arch_RUDDER_SERVO; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\rf_xmtr_rcvr.vhd library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE; use IEEE.electrical_systems.all; use IEEE.mechanical_systems.all; use IEEE.fluidic_systems.all; use IEEE.thermal_systems.all; use IEEE.radiant_systems.all; entity RF_xmtr_rcvr is generic (td : time := 0ns); port ( tdm_in : in std_logic ; tdm_out : out std_logic ); end RF_xmtr_rcvr; architecture behavioral of RF_xmtr_rcvr is begin tdm_out <= tdm_in after td; end; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\stick.vhd -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Electrical sinusoidal voltage source (stick.vhd) LIBRARY IEEE; USE IEEE.MATH_REAL.ALL; -- Use proposed IEEE natures and packages LIBRARY IEEE; USE IEEE.ELECTRICAL_SYSTEMS.ALL; ENTITY stick IS -- Initialize parameters GENERIC ( freq : real; -- frequency, [Hertz] amplitude : real; -- amplitude, [Volt] phase : real := 0.0; -- initial phase, [Degree] offset : real := 0.0; -- DC value, [Volt] df : real := 0.0; -- damping factor, [1/second] ac_mag : real := 1.0; -- AC magnitude, [Volt] ac_phase : real := 0.0); -- AC phase, [Degree] -- Define ports as electrical terminals PORT ( TERMINAL v_out : ELECTRICAL); END ENTITY stick; -- Ideal Architecture ARCHITECTURE ideal OF stick IS -- Declare Branch Quantities QUANTITY v ACROSS i THROUGH v_out TO electrical_ref; -- Declare Quantity for Phase in radians (calculated below) QUANTITY phase_rad : real; -- Declare Quantity in frequency domain for AC analysis QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0; BEGIN -- Convert phase to radians phase_rad == math_2_pi *(freq * NOW + phase / 360.0); IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df); ELSE v == ac_spec; -- used for Frequency (AC) analysis END USE; END ARCHITECTURE ideal; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\rudder.vhd ------------------------------------------------------------------------------- -- Rudder Model (Rotational Spring) -- -- Transfer Function: -- -- torq = -k*(theta - theta_0) -- -- Where theta = input rotational angle, -- torq = output rotational angle, -- theta_0 = reference angle ------------------------------------------------------------------------------- -- Use IEEE_proposed instead of disciplines library IEEE; use ieee.math_real.all; library IEEE; use IEEE.mechanical_systems.all; entity rudder is generic ( k : real := 1.0; -- Spring constant theta_0 : real := 0.0); port ( terminal rot : rotational); -- input rotational angle end entity rudder; architecture bhv of rudder is QUANTITY theta across torq through rot TO ROTATIONAL_REF; begin -- bhv torq == k*(theta - theta_0); -- Convert force to torque end bhv; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\tran_linkage.vhd library IEEE; use IEEE.std_logic_arith.all; library IEEE; use IEEE.mechanical_systems.all; entity tran_linkage is port ( terminal p1, p2 : translational ); begin end tran_linkage; architecture a1 of tran_linkage is QUANTITY pos_1 across frc_1 through p1 TO translational_ref; QUANTITY pos_2 across frc_2 through p2 TO translational_ref; begin pos_2 == pos_1; -- Pass position frc_2 == -frc_1; -- Pass force end; -- -- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\Rotational/stop_r.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : stop_r.vhd -- Author : Mentor Graphics -- Created : 2001/10/10 -- Last update: 2003-05-13 ------------------------------------------------------------------------------- -- Description: Mechanical Hard Stop (ROTATIONAL domain) ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created -- 2002/05/24 1.1 Mentor Graphics Changed constants to type angle -- 2003-04-02 1.2 Mentor Graphics IEEE package update v1.3 ------------------------------------------------------------------------------- library IEEE; use IEEE.MATH_REAL.all; use IEEE.MECHANICAL_SYSTEMS.all; entity stop_r is generic ( k_stop : stiffness; -- Stiffness of hard stop [N/m] damp_stop : damping := 1.0e-9; -- Damping of hard stop [N-sec/m] ang_max : angle; -- Max angle [Radians] ang_min : angle := 0.0 -- Min angle [Radians] ); port ( terminal ang1, ang2 : rotational); end entity stop_r; architecture ideal of stop_r is quantity velocity : velocity; quantity ang across trq through ang1 to ang2; begin velocity == ang'dot; if ang'above(ang_max) use trq == k_stop * (ang - ang_max) + (damp_stop * velocity); elsif ang'above(ang_min) use trq == 0.0; else trq == k_stop * (ang - ang_min) + (damp_stop * velocity); end use; break on ang'above(ang_min), ang'above(ang_max); end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- -- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\MixedTechnology/DCMotor_rv.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : DCMotor_rv.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2003-05-23 ------------------------------------------------------------------------------- -- Description: Basic DC Motor with output of type ROTATIONAL_VELOCITY ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- -- Use proposed IEEE natures and packages library IEEE; use IEEE.mechanical_systems.all; use IEEE.electrical_systems.all; entity DCMotor_rv is generic ( r_wind : resistance; -- Motor winding resistance [Ohm] kt : real; -- Torque coefficient [N*m/Amp] l : inductance; -- Winding inductance [Henrys] d : real; -- Damping coefficient [N*m/(rad/sec)] j : moment_inertia); -- Moment of inertia [kg*meter**2] port (terminal p1, p2 : electrical; terminal shaft_rotv : rotational_velocity); end entity DCMotor_rv; ------------------------------------------------------------------------------- -- Basic Architecture -- Motor equations: V = Kt*W + I*Rwind + L*dI/dt -- T = -Kt*I + D*W + J*dW/dt ------------------------------------------------------------------------------- architecture basic of DCMotor_rv is quantity v across i through p1 to p2; quantity w across torq through shaft_rotv to rotational_velocity_ref; begin torq == -1.0*kt*i + d*w + j*w'dot; v == kt*w + i*r_wind + l*i'dot; end architecture basic; ------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\horn_t2r.vhd ------------------------------------------------------------------------------- -- Control Horn for Rudder Control (mechanical implementation) -- -- Transfer Function: -- -- theta = arcsin(pos/R) -- -- Where pos = input translational position, -- R = horn radius, -- theta = output rotational angle ------------------------------------------------------------------------------- -- Use IEEE_proposed instead of disciplines library IEEE; use ieee.math_real.all; library IEEE; use IEEE.mechanical_systems.all; entity horn_t2r is generic ( R : real := 1.0); -- Rudder horn radius port ( terminal pos : translational; -- input translational position port terminal theta : rotational); -- output angular position port end entity horn_t2r ; architecture bhv of horn_t2r is QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF; QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF; begin -- bhv rot == arcsin(tran/R); -- Convert translational to angle rot_tq == -tran_frc*R; -- Convert force to torque end bhv; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\horn_r2t.vhd ------------------------------------------------------------------------------- -- Control Horn for Rudder Control (mechanical implementation) -- -- Transfer Function: -- -- tran = R*sin(rot) -- -- Where pos = output translational position, -- R = horn radius, -- theta = input rotational angle ------------------------------------------------------------------------------- library IEEE; use ieee.math_real.all; library IEEE; use IEEE.mechanical_systems.all; entity horn_r2t is generic ( R : real := 1.0); -- horn radius port ( terminal theta : ROTATIONAL; -- input angular position port terminal pos : TRANSLATIONAL); -- output translational position port end entity horn_r2t; architecture bhv of horn_r2t is QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF; QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF; begin -- bhv tran == R*sin(rot); -- Convert angle in to translational out tran_frc == -rot_tq/R; -- Convert torque in to force out end bhv; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\rot2v.vhd ------------------------------------------------------------------------------- -- Rotational to Electrical Converter -- ------------------------------------------------------------------------------- library IEEE; use ieee.math_real.all; use IEEE.mechanical_systems.all; use IEEE.electrical_systems.all; entity rot2v is generic ( k : real := 1.0); -- optional gain port ( terminal input : rotational; -- input terminal terminal output : electrical); -- output terminal end entity rot2v ; architecture bhv of rot2v is quantity rot_in across input to rotational_ref; -- Converter's input branch quantity v_out across out_i through output to electrical_ref;-- Converter's output branch begin -- bhv v_out == k*rot_in; end bhv; -- -- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\Electrical/v_constant.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : v_constant.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2003-10-02 ------------------------------------------------------------------------------- -- Description: Constant Voltage Source -- Includes Frequency Domain settings ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- library IEEE; use IEEE.MATH_REAL.all; -- Use IEEE natures and packages use IEEE.electrical_systems.all; entity v_constant is generic ( level : voltage; -- Constant voltage value [Volts] ac_mag : voltage := 0.0; -- AC magnitude [Volts] ac_phase : real := 0.0); -- AC phase [Degrees] port ( terminal pos, neg : electrical); end entity v_constant; ------------------------------------------------------------------------------- -- Ideal Architecture (I = constant) ------------------------------------------------------------------------------- architecture ideal of v_constant is -- Declare Branch Quantities quantity v across i through pos to neg; -- Declare quantity in frequency domain for AC analysis quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0; begin if domain = quiescent_domain or domain = time_domain use v == level; else v == ac_spec; -- used for Frequency (AC) analysis end use; end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\lpf_1_e.vhd ------------------------------------------------------------------------------- -- First Order Lowpass filter -- -- Transfer Function: -- -- w1 -- H(s) = k * ----------- -- s + w1 -- -- DC Gain = k ------------------------------------------------------------------------------- -- Use IEEE_proposed instead of disciplines library IEEE; use IEEE.electrical_systems.all; library IEEE; use ieee.math_real.all; entity lpf_1_e is generic ( fp : real; -- pole freq in Hertz gain : real := 1.0); -- filter gain port ( terminal input: electrical; terminal output: electrical); end entity lpf_1_e; architecture simple of lpf_1_e is QUANTITY vin ACROSS input TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; constant wp : real := math_2_pi*fp; constant num : real_vector := (0 => wp*gain); -- 0=> is needed to give -- index when only a single -- element is used. constant den : real_vector := (wp, 1.0); quantity vin_temp : real; begin vin_temp == vin; -- intermediate variable (vin) req'd for now vout == vin_temp'ltf(num, den); end architecture simple; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\integ_1_e.vhd ------------------------------------------------------------------------------- -- Integrator -- -- Transfer Function: -- -- k -- H(s) = --------- -- s -- ------------------------------------------------------------------------------- -- Use IEEE_proposed instead of disciplines library IEEE; use IEEE.electrical_systems.all; library IEEE; use ieee.math_real.all; entity integ_1_e is generic ( k: real := 1.0; -- Gain -- init: real := real'low); -- Initial value of output init: real := 0.0); -- Initial value of output port (terminal input: electrical; terminal output: electrical); end entity integ_1_e; architecture simple of integ_1_e is QUANTITY vin ACROSS input TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; quantity vin_temp : real; begin vin_temp == vin; -- IF domain = QUIESCENT_DOMAIN AND init /= real'low USE IF domain = QUIESCENT_DOMAIN AND init /= 0.0 USE vout == init; ELSE vout == k*vin_temp'INTEG; END USE; end architecture simple; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\genhdl\airplane_hcl\hcl.vhd -- genhdl\airplane_hcl/hcl.vhd -- Generated by SystemVision netlister 1.0 build 2003.325.1 -- File created Sat Nov 22 14:06:20 2003 library edulib; library ieee; library mgc_ams; use ieee.electrical_systems.all; use ieee.fluidic_systems.all; use ieee.mechanical_systems.all; use ieee.radiant_systems.all; use ieee.std_logic_1164.all; use ieee.thermal_systems.all; use mgc_ams.conversion.all; use work.all; entity HCL is port( terminal OUTPUT : ELECTRICAL; terminal PLANE_POS : ELECTRICAL ); end entity HCL; architecture arch_HCL of HCL is terminal XSIG010001: ELECTRICAL; terminal XSIG010002: ELECTRICAL; terminal XSIG010003: ELECTRICAL; terminal HCL_ERR_IN: ELECTRICAL; terminal HEADING: ELECTRICAL; component SUM2_E generic( K1 : REAL:=1.0; K2 : REAL:=1.0 ); port( terminal IN1 : ELECTRICAL; terminal IN2 : ELECTRICAL; terminal OUTPUT : ELECTRICAL ); end component SUM2_E; component LPF_1_E generic( FP : REAL; GAIN : REAL:=1.0 ); port( terminal INPUT : ELECTRICAL; terminal OUTPUT : ELECTRICAL ); end component LPF_1_E; component INTEG_1_E generic( INIT : REAL:=0.0; K : REAL:=1.0 ); port( terminal INPUT : ELECTRICAL; terminal OUTPUT : ELECTRICAL ); end component INTEG_1_E; component GAIN_E generic( K : REAL:=1.0 ); port( terminal INPUT : ELECTRICAL; terminal OUTPUT : ELECTRICAL ); end component GAIN_E; component V_CONSTANT generic( AC_MAG : VOLTAGE:=0.0; AC_PHASE : REAL:=0.0; LEVEL : VOLTAGE ); port( terminal POS : ELECTRICAL; terminal NEG : ELECTRICAL ); end component V_CONSTANT; for SUM1: SUM2_E use entity WORK.SUM2_E; for SET_SRC: V_CONSTANT use entity EDULIB.V_CONSTANT; for SUM2: SUM2_E use entity WORK.SUM2_E; for LOWPASS: LPF_1_E use entity WORK.LPF_1_E; for INTEG: INTEG_1_E use entity WORK.INTEG_1_E; for PROP_GAIN: GAIN_E use entity WORK.GAIN_E; begin SUM1 : SUM2_E port map ( IN1 => HEADING, IN2 => PLANE_POS, OUTPUT => HCL_ERR_IN ); SET_SRC : V_CONSTANT generic map ( LEVEL => 0.0 ) port map ( POS => HEADING, NEG => ELECTRICAL_REF ); SUM2 : SUM2_E port map ( IN1 => XSIG010002, IN2 => XSIG010003, OUTPUT => XSIG010001 ); LOWPASS : LPF_1_E generic map ( FP => 4.0 ) port map ( INPUT => XSIG010001, OUTPUT => OUTPUT ); INTEG : INTEG_1_E generic map ( INIT => 0.0, K => 0.1 ) port map ( INPUT => HCL_ERR_IN, OUTPUT => XSIG010003 ); PROP_GAIN : GAIN_E generic map ( K => 1.0 ) port map ( INPUT => HCL_ERR_IN, OUTPUT => XSIG010002 ); end architecture arch_HCL; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\gear_rv_r.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : gear_rv_r.vhd -- Author : Mentor Graphics -- Created : 2001/10/10 -- Last update: 2001/10/10 ------------------------------------------------------------------------------- -- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains) ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/10/10 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- library IEEE; use IEEE.mechanical_systems.all; entity gear_rv_r is generic( ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1) -- Note: can be negative, if shaft polarity changes port ( terminal rotv1 : ROTATIONAL_VELOCITY; terminal rot2 : rotational); end entity gear_rv_r; ------------------------------------------------------------------------------- -- Ideal Architecture ------------------------------------------------------------------------------- architecture ideal of gear_rv_r is quantity w1 across torq_vel through rotv1 to ROTATIONAL_VELOCITY_REF; -- quantity w2 across torq2 through rotv2 to rotational_v_ref; quantity theta across torq_ang through rot2 to rotational_ref; begin -- w2 == w1*ratio; theta == ratio*w1'integ; torq_vel == -1.0*torq_ang*ratio; end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- -- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\Electrical/v_PWL.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : v_PWL.vhd -- Author : Mentor Graphics -- Created : 2003-04-09 -- Last update: 2003-05-13 ------------------------------------------------------------------------------- -- Description: Piecewise linear voltage source ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2003-04-09 1.0 Mentor Graphics Created -- 2003-04-18 1.1 Mentor Graphics Added AC analysis code ------------------------------------------------------------------------------- library IEEE; use IEEE.math_real.all; use IEEE.electrical_systems.all; -- The MGC_AMS library contains a "conversion" package that includes the -- time2real_vector conversion function along with the time_vector type -- definition (time_vector type is pending IEEE approval). -- The source file (mgc_ams_additions.vhd) is located in the SystemVision -- install tree. library MGC_AMS; use MGC_AMS.conversion.all; entity v_PWL is generic ( -- default voltage and time data values vdata : real_vector := (0.0, 0.0, 10.0, 10.0, 5.0, 5.0, 0.0); timedata : time_vector := (0 ms, 1 ms, 1.1 ms, 2 ms, 2.1 ms, 3 ms, 3.1 ms); ac_mag : voltage := 1.0; -- AC magnitude [Volts] ac_phase : real := 0.0); -- AC phase [Degrees] port ( terminal pos, neg : electrical ); begin end entity v_PWL; architecture ideal of v_PWL is quantity v across i through pos to neg; -- Declare quantity in frequency domain for AC analysis quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0; -- Convert time_vector to real_vector for use in get_slope function constant n : integer := timedata'LENGTH; constant tdata : real_vector(0 to n-1) := time2real_vector(timedata); signal last_v : real := vdata(0); signal last_time : real := 0.0; signal m : real := 0.0; ------------------------------------------------------------------------------- -- function to progressively calculate slope from voltage and time -- data (both are real_vectors) function get_slope (tdata : in real_vector; vdata : in real_vector; count : in integer) return real is variable m : real; begin if count >= tdata'right then m := 0.0; else assert (tdata(count + 1) /= tdata(count)) report "get_slope: tdata vector has repeated values" severity error; m := (vdata(count + 1) - vdata(count))/(tdata(count + 1) - tdata(count)); end if; return m; end function get_slope; ------------------------------------------------------------------------------- begin -- process to keep track of current time and voltage pair to use in -- slope calculation time_slice : process is variable count : integer := 0; begin wait until domain = time_domain; while count < tdata'right loop m <= get_slope(tdata, vdata, count); -- send real_vectors to get_slope -- function last_v <= vdata(count); -- mark last voltage last_time <= tdata(count); -- mark last time point wait for (timedata(count + 1) - timedata(count)); -- time_vector req'd -- for wait statement count := count + 1; end loop; m <= 0.0; -- flat extrapolation beyond vdata, tdata range last_v <= vdata(vdata'right); -- don't need to assign last_time here as it's not used, since m = 0.0. wait; -- forever end process time_slice; break on last_v; -- force analog time step if domain = quiescent_domain or domain = time_domain use v == m*(NOW - last_time) + last_v; -- slope-intercept equation y=mx+b else v == ac_spec; -- used for Frequency (AC) analysis end use; end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- -- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\Electrical/v_pulse.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : v_pulse.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2003-05-13 ------------------------------------------------------------------------------- -- Description: Voltage Pulse Source -- Includes Frequency Domain settings ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created -- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type -- time. Uses time2real function. -- Pulsewidth no longer includes -- rise and fall times. -- 2002-06-06 1.2 Mentor Graphics Fixed bug when delay=0 ------------------------------------------------------------------------------- library IEEE; use IEEE.MATH_REAL.all; -- Use IEEE natures and packages use IEEE.electrical_systems.all; entity v_pulse is generic ( initial : voltage := 0.0; -- initial value [Volts] pulse : voltage; -- pulsed value [Volts] ti2p : time := 1ns; -- initial to pulse [Sec] tp2i : time := 1ns; -- pulse to initial [Sec] delay : time := 0ms; -- delay time [Sec] width : time; -- duration of pulse [Sec] period : time; -- period [Sec] ac_mag : voltage := 1.0; -- AC magnitude [Volts] ac_phase : real := 0.0); -- AC phase [Degrees] port ( terminal pos, neg : electrical); end entity v_pulse; ------------------------------------------------------------------------------- -- Ideal Architecture ------------------------------------------------------------------------------- architecture ideal of v_pulse is -- Declare Through and Across Branch Quantities quantity v across i through pos to neg; -- Declare quantity in frequency domain for AC analysis quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0; -- Signal used in CreateEvent process below signal pulse_signal : voltage := initial; -- Function to convert numbers of type TIME to type REAL function time2real(tt : time) return real is begin return time'pos(tt) * 1.0e-15; end time2real; -- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute) constant ri2p : real := time2real(ti2p); constant rp2i : real := time2real(tp2i); begin if domain = quiescent_domain or domain = time_domain use v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions else v == ac_spec; -- used for Frequency (AC) analysis end use; -- purpose: Create events to define pulse shape -- type : combinational -- inputs : -- outputs: pulse_signal CreateEvent : process begin wait until domain = time_domain; -- Run process in Time Domain only wait for delay; loop pulse_signal <= pulse; wait for (width + ti2p); pulse_signal <= initial; wait for (period - width - ti2p); end loop; end process CreateEvent; end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- -- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\Electrical/resistor.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : resistor.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2002-05-24 ------------------------------------------------------------------------------- -- Description: Electrical Resistor ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- -- Use proposed IEEE natures and packages library IEEE; use IEEE.electrical_systems.all; entity resistor is generic ( res : resistance); -- resistance (no initial value) port ( terminal p1, p2 : electrical); end entity resistor; ------------------------------------------------------------------------------- -- Ideal Architecture (V = I*R) ------------------------------------------------------------------------------- architecture ideal of resistor is quantity v across i through p1 to p2; begin -- Fundamental equation v == i*res; end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\genhdl\airplane_hcl\plane_pos_src.vhd -- genhdl\airplane_hcl/plane_pos_src.vhd -- Generated by SystemVision netlister 1.0 build 2003.325.1 -- File created Sat Nov 22 14:06:20 2003 library edulib; library ieee; library mgc_ams; use ieee.electrical_systems.all; use ieee.fluidic_systems.all; use ieee.mechanical_systems.all; use ieee.radiant_systems.all; use ieee.std_logic_1164.all; use ieee.thermal_systems.all; use mgc_ams.conversion.all; use work.all; entity PLANE_POS_SRC is port( terminal PLANE_POS : ELECTRICAL; terminal RUDDER_FB : ELECTRICAL ); end entity PLANE_POS_SRC; architecture arch_PLANE_POS_SRC of PLANE_POS_SRC is terminal WIND: ELECTRICAL; terminal WIND_NEG: ELECTRICAL; terminal XSIG010020: ELECTRICAL; terminal PLANE_SUM_OUT: ELECTRICAL; terminal FLIGHT_DEVIATION: ELECTRICAL; component SUM2_E generic( K1 : REAL:=1.0; K2 : REAL:=1.0 ); port( terminal IN1 : ELECTRICAL; terminal IN2 : ELECTRICAL; terminal OUTPUT : ELECTRICAL ); end component SUM2_E; component V_PULSE generic( AC_MAG : VOLTAGE:=0.0; AC_PHASE : REAL:=0.0; DELAY : TIME:=0 MS; INITIAL : VOLTAGE:=0.0; PERIOD : TIME; PULSE : VOLTAGE; TI2P : TIME:=1 NS; TP2I : TIME:=1 NS; WIDTH : TIME ); port( terminal POS : ELECTRICAL; terminal NEG : ELECTRICAL ); end component V_PULSE; component GAIN_E generic( K : REAL:=1.0 ); port( terminal INPUT : ELECTRICAL; terminal OUTPUT : ELECTRICAL ); end component GAIN_E; component V_PWL generic( AC_MAG : VOLTAGE:=0.0; AC_PHASE : REAL:=0.0; TIMEDATA : TIME_VECTOR:=(0 MS,1 MS,1.1 MS,2 MS,2.1 MS,3 MS,3.1 MS); VDATA : REAL_VECTOR:=(0.0, 0.0, 10.0, 10.0, 5.0, 5.0, 0.0) ); port( terminal POS : ELECTRICAL; terminal NEG : ELECTRICAL ); end component V_PWL; component RESISTOR generic( RES : RESISTANCE ); port( terminal P1 : ELECTRICAL; terminal P2 : ELECTRICAL ); end component RESISTOR; for PWL_WIND: V_PWL use entity EDULIB.V_PWL; for V3: V_PULSE use entity EDULIB.V_PULSE; for R2: RESISTOR use entity EDULIB.RESISTOR(IDEAL); for SUM2: SUM2_E use entity WORK.SUM2_E; for WIND_NEG_GAIN: GAIN_E use entity WORK.GAIN_E; for DIR_OUT: GAIN_E use entity WORK.GAIN_E; for SUM1: SUM2_E use entity WORK.SUM2_E; begin PWL_WIND : V_PWL generic map ( TIMEDATA => (0 MS, 100 MS, 110 MS, 500 MS, 510 MS, 800 MS, 810 MS), VDATA => (0.0,0.0,-2.4,-2.4,-4.7,-4.7,0.0) ) port map ( POS => WIND, NEG => ELECTRICAL_REF ); V3 : V_PULSE generic map ( DELAY => 100 MS, INITIAL => 0.0, PERIOD => 3 SEC, PULSE => -4.8, TI2P => 1 SEC, TP2I => 1 SEC, WIDTH => 100 MS ) port map ( POS => XSIG010020, NEG => ELECTRICAL_REF ); R2 : RESISTOR generic map ( RES => 10.0E3 ) port map ( P1 => ELECTRICAL_REF, P2 => XSIG010020 ); SUM2 : SUM2_E generic map ( K1 => 1.0, K2 => 1.89 ) port map ( IN1 => WIND, IN2 => RUDDER_FB, OUTPUT => FLIGHT_DEVIATION ); WIND_NEG_GAIN : GAIN_E generic map ( K => -1.0 ) port map ( INPUT => WIND, OUTPUT => WIND_NEG ); DIR_OUT : GAIN_E generic map ( K => -1.0 ) port map ( INPUT => PLANE_SUM_OUT, OUTPUT => PLANE_POS ); SUM1 : SUM2_E generic map ( K1 => 1.0 ) port map ( IN1 => WIND, IN2 => RUDDER_FB, OUTPUT => PLANE_SUM_OUT ); end architecture arch_PLANE_POS_SRC; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\level_set.vhd -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- level_set.vhd -- Set digital output "level" with parameter "logic_val" (default is '1') LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY level_set IS GENERIC ( logic_val : std_logic := '1'); PORT ( level : OUT std_logic); END ENTITY level_set; -- Simple architecture ARCHITECTURE ideal OF level_set IS BEGIN level <= logic_val; END ARCHITECTURE ideal; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\inverter.vhd -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Inverter LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY inverter IS GENERIC ( delay : time := 0 ns); -- Delay time PORT ( input : IN std_logic; output : OUT std_logic); END ENTITY inverter; ARCHITECTURE ideal OF inverter IS BEGIN output <= NOT input AFTER delay; END ARCHITECTURE ideal; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\counter_preload.vhd -- This is a down counter with pre-loadable inputs. It functions as follows: -- A digital word is loaded into the data_in port with load='1'; -- When cnt_en='1' and counter value > 0, tc is set high and the counter starts decrementing -- from the integer value of the loaded input vector. This continues until the counter -- reaches 0, at which time the tc pin goes low. -- Note that this counter is configured for ascending bit values (LSB to MSB). If descending -- bit values are to be used, the 'range rather than the 'reverse_range attribute should be used -- for the bit_vector to integer algorithm. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity counter_preload is generic (Nbits : integer := 12); port ( data_in : in std_logic_vector(0 to (Nbits-1)) ; -- User-defined bus width clk : in std_logic ; -- Counter clock load : in std_logic := '0'; -- Parallel load (rising edge) cnt_en : in std_logic := '0'; -- Counter enable (decrement count) tc : out std_logic := '0' -- High while count is in progress ); end counter_preload; architecture behavioral of counter_preload is begin count_proc : process(load, cnt_en, clk) is variable result : integer := 0; -- Vector to integer intermediate calc. variable count : bit_vector(0 to (Nbits-1)); -- Bit_vector version of input bus begin if rising_edge(load) then -- When load rising edge occurs... result := 0; count := To_bitvector(data_in); -- Convert to bit_vector type for index in count'reverse_range loop result := result*2 + bit'pos(count(index)); -- Calc. "weight" of bit_vector end loop; elsif cnt_en = '1' and result > 0 then -- OK to count down? if rising_edge(clk) then -- Decrement once each clock cycle tc <= '1'; -- Output is high while count in progress result := result - 1; -- Decrement count end if; else if rising_edge(clk) then -- tc=0 all other times tc <= '0'; end if; end if; end process count_proc; end behavioral; -- -- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\MixedSignal/d2a_bit.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : d2a_bit.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2003-05-13 ------------------------------------------------------------------------------- -- Description: Ideal one bit D/A converter ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created -- 2001/06/16 1.1 Mentor Graphics Added t_ramp parameter ------------------------------------------------------------------------------- library IEEE; use IEEE.electrical_systems.all; use IEEE.std_logic_1164.all; entity d2a_bit is generic (vlow : voltage := 0.0; -- output high voltage vhigh : voltage := 5.0; -- output low voltage t_ramp : real := 1.0e-9); -- Ramp time from vlow to vhigh -- and vhigh to vlow port (D : in std_logic; -- digital (std_logic) intout terminal A : electrical); -- analog (electrical) output end entity d2a_bit; ------------------------------------------------------------------------------- -- Ideal architecture ------------------------------------------------------------------------------- architecture ideal of d2a_bit is quantity vout across iout through A to electrical_ref; signal vin : voltage := 0.0; begin vin <= vhigh when D = '1' else vlow; -- Use 'RAMP for discontinuous signal vout == vin'ramp(t_ramp); end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\clock_duty.vhd -- This digital clock allows user to specify the duty cycle using -- the parameters "on_time" and "off_time" library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE; use IEEE.electrical_systems.all; use IEEE.mechanical_systems.all; use IEEE.fluidic_systems.all; use IEEE.thermal_systems.all; use IEEE.radiant_systems.all; ENTITY clock_duty IS GENERIC ( on_time : time := 20 us; off_time : time := 19.98 ms ); PORT ( clock_out : OUT std_logic := '0'); END ENTITY clock_duty; ARCHITECTURE ideal OF clock_duty IS BEGIN -- clock process process begin clock_out <= '1'; wait for on_time; clock_out <= '0'; wait for off_time; end process; END ARCHITECTURE ideal; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\clock.vhd -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Digital clock with 50% duty cycle LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY clock IS GENERIC ( period : time); -- Clock period PORT ( clk_out : OUT std_logic); END ENTITY clock; ARCHITECTURE ideal OF clock IS BEGIN -- clock process process begin clk_out <= '0'; wait for period/2; clk_out <= '1'; wait for period/2; end process; END ARCHITECTURE ideal; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\genhdl\airplane_hcl\rc_clk.vhd -- genhdl\airplane_hcl/rc_clk.vhd -- Generated by SystemVision netlister 1.0 build 2003.325.1 -- File created Sat Nov 22 14:06:20 2003 library edulib; library ieee; library mgc_ams; use ieee.electrical_systems.all; use ieee.fluidic_systems.all; use ieee.mechanical_systems.all; use ieee.radiant_systems.all; use ieee.std_logic_1164.all; use ieee.thermal_systems.all; use mgc_ams.conversion.all; use work.all; entity RC_CLK is port( signal CLK_100K : OUT STD_LOGIC; signal CLK_50 : OUT STD_LOGIC; signal CLK_6K : OUT STD_LOGIC ); end entity RC_CLK; architecture arch_RC_CLK of RC_CLK is component CLOCK generic( PERIOD : TIME ); port( signal CLK_OUT : OUT STD_LOGIC ); end component CLOCK; component CLOCK_DUTY generic( OFF_TIME : TIME:=19.98MS; ON_TIME : TIME:=20US ); port( signal CLOCK_OUT : OUT STD_LOGIC ); end component CLOCK_DUTY; for CLK_50HZ: CLOCK_DUTY use entity WORK.CLOCK_DUTY; for CLK_6K_1: CLOCK use entity WORK.CLOCK; for CLK_100K_1: CLOCK use entity WORK.CLOCK; begin CLK_50HZ : CLOCK_DUTY generic map ( OFF_TIME => 19.98 MS, ON_TIME => 20 US ) port map ( CLOCK_OUT => CLK_50 ); CLK_6K_1 : CLOCK generic map ( PERIOD => 150US ) port map ( CLK_OUT => CLK_6K ); CLK_100K_1 : CLOCK generic map ( PERIOD => 10US ) port map ( CLK_OUT => CLK_100K ); end architecture arch_RC_CLK; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\sr_ff.vhd -- Set/reset flip flop -- When S goes high, Q is set high until reset -- When R goes high, Q is set low until set library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE; use IEEE.electrical_systems.all; entity sr_ff is port ( S : in std_logic ; R : in std_logic ; Q : out std_logic ); end sr_ff ; architecture simple of sr_ff is begin set_reset: PROCESS(S, R) IS BEGIN -- assert S='1' nand R='1' -- Warning if both inputs are high -- report "S and R are both active. Use with caution" -- severity warning; if S'event AND S = '1' then Q <= '1'; end if; if R'event AND R = '1' then Q <= '0'; end if; END PROCESS set_reset; end; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\state_mach_rcvr.vhd LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; ENTITY state_mach_rcvr IS PORT ( clk_50 : IN std_logic; clk_100k : IN std_logic; ser_done : IN std_logic; par_det : IN std_logic; frm_det : IN std_logic; clk_6k : IN std_logic; start_pulse : IN std_logic; dly_done : IN std_logic; s2p_rst : OUT std_logic; s2p_en : OUT std_logic; cnt1_en : OUT std_logic; cnt1_load : OUT std_logic; cnt2_en : OUT std_logic; cnt2_load : OUT std_logic; da_latch : OUT std_logic; ser_cnt : OUT std_logic; dly_cnt : OUT std_logic; par_oe : OUT std_logic); END state_mach_rcvr; ARCHITECTURE state_diagram OF state_mach_rcvr IS ATTRIBUTE ENUM_TYPE_ENCODING: STRING; TYPE TYP_state_mach_rcvr_sm1 IS (V_begin, cnt, ch1, rst1, ch2, rst2, cnt_cmp, rst_cnt, s_bit, par1, par2); SIGNAL CS_state_mach_rcvr_sm1, NS_state_mach_rcvr_sm1 : TYP_state_mach_rcvr_sm1; BEGIN sm1: PROCESS (CS_state_mach_rcvr_sm1, clk_50, frm_det, ser_done, start_pulse, dly_done, par_det) BEGIN CASE CS_state_mach_rcvr_sm1 IS WHEN V_begin => cnt1_en <= ('0'); cnt1_load <= ('0'); cnt2_en <= ('0'); cnt2_load <= ('0'); s2p_en <= ('1'); s2p_rst <= ('0'); da_latch <= ('0'); ser_cnt <= ('0'); dly_cnt <= ('0'); par_oe <= ('0'); IF ((frm_det = '1')) THEN NS_state_mach_rcvr_sm1 <= s_bit; ELSE NS_state_mach_rcvr_sm1 <= V_begin; END IF; WHEN cnt => ser_cnt <= ('1'); IF ((ser_done = '1')) THEN NS_state_mach_rcvr_sm1 <= par1; ELSE NS_state_mach_rcvr_sm1 <= cnt; END IF; WHEN ch1 => cnt1_load <= ('1'); ser_cnt <= ('0'); dly_cnt <= ('1'); IF (((start_pulse = '1') AND (dly_done = '1'))) THEN NS_state_mach_rcvr_sm1 <= rst1; ELSE NS_state_mach_rcvr_sm1 <= ch1; END IF; WHEN rst1 => cnt1_load <= ('0'); ser_cnt <= ('1'); dly_cnt <= ('0'); par_oe <= ('0'); IF ((ser_done = '1')) THEN NS_state_mach_rcvr_sm1 <= par2; ELSE NS_state_mach_rcvr_sm1 <= rst1; END IF; WHEN ch2 => cnt2_load <= ('1'); ser_cnt <= ('0'); da_latch <= ('1'); NS_state_mach_rcvr_sm1 <= rst2; WHEN rst2 => cnt2_load <= ('0'); s2p_en <= ('0'); par_oe <= ('0'); da_latch <= ('0'); NS_state_mach_rcvr_sm1 <= cnt_cmp; WHEN cnt_cmp => cnt1_en <= ('1'); cnt2_en <= ('1'); NS_state_mach_rcvr_sm1 <= rst_cnt; WHEN rst_cnt => cnt1_en <= ('0'); cnt2_en <= ('0'); NS_state_mach_rcvr_sm1 <= rst_cnt; WHEN s_bit => IF ((start_pulse = '1')) THEN NS_state_mach_rcvr_sm1 <= cnt; ELSE NS_state_mach_rcvr_sm1 <= s_bit; END IF; WHEN par1 => par_oe <= ('1'); IF ((par_det = '0')) THEN NS_state_mach_rcvr_sm1 <= ch1; ELSIF ((par_det = '1')) THEN NS_state_mach_rcvr_sm1 <= rst1; ELSE NS_state_mach_rcvr_sm1 <= par1; END IF; WHEN par2 => par_oe <= ('1'); IF ((par_det = '0')) THEN NS_state_mach_rcvr_sm1 <= ch2; ELSIF ((par_det = '1')) THEN NS_state_mach_rcvr_sm1 <= rst2; ELSE NS_state_mach_rcvr_sm1 <= par2; END IF; END CASE; END PROCESS; sm1_CTL: PROCESS (clk_100k, clk_50) BEGIN IF (clk_100k'event AND clk_100k='1') THEN IF (clk_50= '1' ) THEN CS_state_mach_rcvr_sm1 <= V_begin; ELSE CS_state_mach_rcvr_sm1 <= NS_state_mach_rcvr_sm1; END IF; END IF; END PROCESS; END state_diagram; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\bit_cnt.vhd -- This model counts the number of input clock transitions and outputs -- a '1' when this number equals the value of the user-defined constant 'count' library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity bit_cnt is generic ( count : integer -- User-defined value to count up to ); port ( bit_in : in std_logic ; clk : in std_logic ; dly_out : out std_logic ); end bit_cnt; architecture behavioral of bit_cnt is begin serial_clock : process is begin wait until bit_in'event AND (bit_in = '1' OR bit_in = 'H'); FOR i IN 0 to count LOOP -- Loop for 'count' clock transitions wait until clk'event AND (clk = '1' OR clk = 'H'); END LOOP ; dly_out <= '1'; -- After count is reached, set output high wait until bit_in'event AND (bit_in = '0' OR bit_in = 'L'); dly_out <= '0'; -- Reset output to '0' on next clock input end process serial_clock; end; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\genhdl\airplane_hcl\sm_cnt_rcvr.vhd -- genhdl\airplane_hcl/sm_cnt_rcvr.vhd -- Generated by SystemVision netlister 1.0 build 2003.325.1 -- File created Sat Nov 22 14:06:20 2003 library edulib; library ieee; library mgc_ams; use ieee.electrical_systems.all; use ieee.fluidic_systems.all; use ieee.mechanical_systems.all; use ieee.radiant_systems.all; use ieee.std_logic_1164.all; use ieee.thermal_systems.all; use mgc_ams.conversion.all; use work.all; entity SM_CNT_RCVR is port( signal CLK_100K : IN STD_LOGIC; signal CLK_50 : IN STD_LOGIC; signal CLK_6K : IN STD_LOGIC; signal CNT1_EN : OUT STD_LOGIC; signal CNT1_LOAD : OUT STD_LOGIC; signal CNT2_EN : OUT STD_LOGIC; signal CNT2_LOAD : OUT STD_LOGIC; signal DA_LATCH : OUT STD_LOGIC; signal FRM_DET : IN STD_LOGIC; signal PAR_DET : IN STD_LOGIC; signal PAR_OE : OUT STD_LOGIC; signal S2P_EN : OUT STD_LOGIC; signal S2P_RST : OUT STD_LOGIC; signal START_PULSE : IN STD_LOGIC ); end entity SM_CNT_RCVR; architecture arch_SM_CNT_RCVR of SM_CNT_RCVR is signal XSIG010145: STD_LOGIC; signal XSIG010002: STD_LOGIC; signal XSIG010146: STD_LOGIC; signal SER_CNT: STD_LOGIC; component BIT_CNT generic( COUNT : INTEGER ); port( signal BIT_IN : IN STD_LOGIC; signal CLK : IN STD_LOGIC; signal DLY_OUT : OUT STD_LOGIC ); end component BIT_CNT; component STATE_MACH_RCVR port( signal CLK_100K : IN STD_LOGIC; signal CLK_50 : IN STD_LOGIC; signal CLK_6K : IN STD_LOGIC; signal CNT1_EN : OUT STD_LOGIC; signal CNT1_LOAD : OUT STD_LOGIC; signal CNT2_EN : OUT STD_LOGIC; signal CNT2_LOAD : OUT STD_LOGIC; signal DA_LATCH : OUT STD_LOGIC; signal DLY_CNT : OUT STD_LOGIC; signal DLY_DONE : IN STD_LOGIC; signal FRM_DET : IN STD_LOGIC; signal PAR_DET : IN STD_LOGIC; signal PAR_OE : OUT STD_LOGIC; signal S2P_EN : OUT STD_LOGIC; signal S2P_RST : OUT STD_LOGIC; signal SER_CNT : OUT STD_LOGIC; signal SER_DONE : IN STD_LOGIC; signal START_PULSE : IN STD_LOGIC ); end component STATE_MACH_RCVR; for STATE_MACH_RCVR9: STATE_MACH_RCVR use entity WORK.STATE_MACH_RCVR; for BIT_CNT4: BIT_CNT use entity WORK.BIT_CNT; for BIT_CNT3: BIT_CNT use entity WORK.BIT_CNT; begin STATE_MACH_RCVR9 : STATE_MACH_RCVR port map ( CLK_100K => CLK_100K, CLK_50 => CLK_50, CLK_6K => CLK_6K, CNT1_EN => CNT1_EN, CNT1_LOAD => CNT1_LOAD, CNT2_EN => CNT2_EN, CNT2_LOAD => CNT2_LOAD, DA_LATCH => DA_LATCH, DLY_CNT => XSIG010145, DLY_DONE => XSIG010146, FRM_DET => FRM_DET, PAR_DET => PAR_DET, PAR_OE => PAR_OE, S2P_EN => S2P_EN, S2P_RST => S2P_RST, SER_CNT => SER_CNT, SER_DONE => XSIG010002, START_PULSE => START_PULSE ); BIT_CNT4 : BIT_CNT generic map ( COUNT => 10 ) port map ( BIT_IN => SER_CNT, CLK => CLK_6K, DLY_OUT => XSIG010002 ); BIT_CNT3 : BIT_CNT generic map ( COUNT => 2 ) port map ( BIT_IN => XSIG010145, CLK => CLK_6K, DLY_OUT => XSIG010146 ); end architecture arch_SM_CNT_RCVR; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\d2a_nbit.vhd library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE; use IEEE.electrical_systems.all; ENTITY d2a_nbit IS GENERIC ( vmax : real := 5.0; -- High output vmin : real := 0.0; -- Low output high_bit : integer := 9; -- High end of bit range for D/A low_bit : integer := 0); -- Low end of bit range for D/A PORT ( SIGNAL bus_in : IN STD_LOGIC_VECTOR(low_bit to high_bit); -- variable width vector input SIGNAL latch : IN STD_LOGIC; TERMINAL ana_out : electrical); -- analog output END ENTITY d2a_nbit ; ARCHITECTURE behavioral OF d2a_nbit IS SIGNAL sout : real := 0.0; QUANTITY vout across iout through ana_out TO electrical_ref; BEGIN -- ARCHITECTURE behavioral proc : PROCESS VARIABLE v_sum : real; -- Sum of voltage contribution from each bit VARIABLE delt_v : real; -- Represents the voltage value of each bit BEGIN WAIT UNTIL (latch'event and latch = '1'); -- Begin when latch goes high v_sum := vmin; delt_v := vmax - vmin; FOR i IN high_bit DOWNTO low_bit LOOP -- Perform the conversions delt_v := delt_v / 2.0; IF bus_in(i) = '1' OR bus_in(i) = 'H' THEN v_sum := v_sum + delt_v; END IF; END LOOP; sout <= v_sum; END PROCESS; vout == sout'ramp(100.0E-9); -- Ensure continuous transition between levels END ARCHITECTURE behavioral; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\and2.vhd -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Two input AND gate LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY and2 IS GENERIC ( delay : time := 0 ns); -- Delay time PORT ( in1, in2 : IN std_logic; output : OUT std_logic); END ENTITY and2; ARCHITECTURE ideal OF and2 IS BEGIN output <= in1 AND in2 AFTER delay; END ARCHITECTURE ideal; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\xor2.vhd -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Two input XOR gate LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY xor2 IS GENERIC ( delay : time := 0 ns); -- Delay time PORT ( in1, in2 : IN std_logic; output : OUT std_logic); END ENTITY xor2; ARCHITECTURE ideal OF xor2 IS BEGIN output <= in1 XOR in2 AFTER delay; END ARCHITECTURE ideal; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\genhdl\airplane_hcl\parity_det.vhd -- genhdl\airplane_hcl/parity_det.vhd -- Generated by SystemVision netlister 1.0 build 2003.325.1 -- File created Sat Nov 22 14:06:20 2003 library edulib; library ieee; library mgc_ams; use ieee.electrical_systems.all; use ieee.fluidic_systems.all; use ieee.mechanical_systems.all; use ieee.radiant_systems.all; use ieee.std_logic_1164.all; use ieee.thermal_systems.all; use mgc_ams.conversion.all; use work.all; entity PARITY_DET is port( signal BUS_IN_0_11_Port : IN STD_LOGIC_VECTOR(0 to 11); signal OE : IN STD_LOGIC; signal PAR_BIT : OUT STD_LOGIC ); end entity PARITY_DET; architecture arch_PARITY_DET of PARITY_DET is signal XSIG010011: STD_LOGIC; signal XSIG010012: STD_LOGIC; signal XSIG010057: STD_LOGIC; signal XSIG010013: STD_LOGIC; signal XSIG010014: STD_LOGIC; signal XSIG010015: STD_LOGIC; signal XSIG010016: STD_LOGIC; signal XSIG010017: STD_LOGIC; signal XSIG010019: STD_LOGIC; signal XSIG010010: STD_LOGIC; component XOR2 generic( DELAY : TIME:=0NS ); port( signal IN1 : IN STD_LOGIC; signal IN2 : IN STD_LOGIC; signal OUTPUT : OUT STD_LOGIC ); end component XOR2; component AND2 generic( DELAY : TIME:=0NS ); port( signal IN1 : IN STD_LOGIC; signal IN2 : IN STD_LOGIC; signal OUTPUT : OUT STD_LOGIC ); end component AND2; for XCMP12: AND2 use entity WORK.AND2; for XCMP10: XOR2 use entity WORK.XOR2; for XCMP9: XOR2 use entity WORK.XOR2; for XCMP8: XOR2 use entity WORK.XOR2; for XCMP7: XOR2 use entity WORK.XOR2; for XCMP6: XOR2 use entity WORK.XOR2; for XCMP5: XOR2 use entity WORK.XOR2; for XCMP4: XOR2 use entity WORK.XOR2; for XCMP3: XOR2 use entity WORK.XOR2; for XCMP2: XOR2 use entity WORK.XOR2; for XCMP1: XOR2 use entity WORK.XOR2; begin XCMP12 : AND2 port map ( IN1 => OE, IN2 => XSIG010057, OUTPUT => PAR_BIT ); XCMP10 : XOR2 port map ( IN1 => XSIG010019, IN2 => BUS_IN_0_11_Port(0), OUTPUT => XSIG010057 ); XCMP9 : XOR2 port map ( IN1 => XSIG010017, IN2 => XSIG010016, OUTPUT => XSIG010019 ); XCMP8 : XOR2 port map ( IN1 => XSIG010014, IN2 => XSIG010015, OUTPUT => XSIG010017 ); XCMP7 : XOR2 port map ( IN1 => XSIG010012, IN2 => XSIG010013, OUTPUT => XSIG010015 ); XCMP6 : XOR2 port map ( IN1 => XSIG010010, IN2 => XSIG010011, OUTPUT => XSIG010014 ); XCMP5 : XOR2 port map ( IN1 => BUS_IN_0_11_Port(9), IN2 => BUS_IN_0_11_Port(10), OUTPUT => XSIG010016 ); XCMP4 : XOR2 port map ( IN1 => BUS_IN_0_11_Port(7), IN2 => BUS_IN_0_11_Port(8), OUTPUT => XSIG010013 ); XCMP3 : XOR2 port map ( IN1 => BUS_IN_0_11_Port(5), IN2 => BUS_IN_0_11_Port(6), OUTPUT => XSIG010012 ); XCMP2 : XOR2 port map ( IN1 => BUS_IN_0_11_Port(3), IN2 => BUS_IN_0_11_Port(4), OUTPUT => XSIG010011 ); XCMP1 : XOR2 port map ( IN1 => BUS_IN_0_11_Port(1), IN2 => BUS_IN_0_11_Port(2), OUTPUT => XSIG010010 ); end architecture arch_PARITY_DET; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\s2p_shift_reg.vhd -- Special-purpose serial to parallel shift register -- This component shifts serial input bitstream data directly to the output with each clock cycle. -- This is done so the Frame detector can keep a "running tab" on the input bitstream with the -- rising edge of each clock. When the proper initial frame sequence is recognized, the data is -- latched and processed. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity s2p_shift_reg is port ( par_out : out std_logic_vector(0 to 11) := "ZZZZZZZZZZZZ"; clk : in std_logic ; load_en : in std_logic ; ser_in : in std_logic ; reset : in std_logic ); end entity s2p_shift_reg; architecture beahvioral of s2p_shift_reg is signal tmp : std_logic_vector(0 to 11); -- This signal is used to avoid pin-pin assignments, -- which requires par_out to be of type inout. begin sr_sm: process (load_en, clk, reset, ser_in) begin if (reset = '1' and load_en = '1') then par_out <= "000000000000"; -- Reset the parallel data out elsif (reset = '0' and load_en = '1') then -- Shift when load_en is high, and if (clk'event and clk = '1') then -- Rising clock edge tmp(0) <= ser_in; par_out(0) <= tmp(0); -- output pins always updated from tmp signal for i in 0 to 10 loop tmp(i+1) <= tmp(i); -- Propogate all bits one position par_out(i+1) <= tmp(i+1); end loop; end if; else par_out <= "ZZZZZZZZZZZZ"; -- No change in output. Tri-state if load_en = 0. end if; end process; end; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\frame_det.vhd -- This model ouputs a '1' when a specific bit pattern is encountered -- Otherwise, it outputs a zero library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity frame_det is port ( bus_in : in std_logic_vector (0 to 11); clk : in std_logic; frm_bit : out std_logic := '0' -- Initialize output to zero ); end entity frame_det; architecture simple of frame_det is begin enbl: PROCESS (bus_in, clk) -- Sensitivity list BEGIN if bus_in = "010101010101" then -- This is the pre-defined bit pattern if clk'event AND clk = '0' then -- Output updated synchronously frm_bit <= '1'; end if; else frm_bit <= '0'; end if; END PROCESS; end architecture simple; -- -- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\Digital/buf.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : buf.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2003-04-21 ------------------------------------------------------------------------------- -- Description: Simple Buffer with delay time ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity buf is generic ( delay : time := 0 ns); -- Delay time port ( input : in std_logic; output : out std_logic); end entity buf; architecture ideal of buf is begin output <= input after delay; end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\genhdl\airplane_hcl\tdm_demux_dbg.vhd -- genhdl\airplane_hcl/tdm_demux_dbg.vhd -- Generated by SystemVision netlister 1.0 build 2003.325.1 -- File created Sat Nov 22 14:06:20 2003 library edulib; library ieee; library mgc_ams; use ieee.electrical_systems.all; use ieee.fluidic_systems.all; use ieee.mechanical_systems.all; use ieee.radiant_systems.all; use ieee.std_logic_1164.all; use ieee.thermal_systems.all; use mgc_ams.conversion.all; use work.all; entity TDM_DEMUX_DBG is port( signal CLK_6K : IN STD_LOGIC; signal DA_LATCH : IN STD_LOGIC; signal FRM_DET : OUT STD_LOGIC; signal PAR_DET : OUT STD_LOGIC; signal PAR_OE : IN STD_LOGIC; signal RCVR_BUS_1_10_Port : OUT STD_LOGIC_VECTOR(1 to 10); signal S2P_EN : IN STD_LOGIC; signal S2P_RST : IN STD_LOGIC; signal START_BIT : OUT STD_LOGIC; signal TDM_IN : IN STD_LOGIC ); end entity TDM_DEMUX_DBG; architecture arch_TDM_DEMUX_DBG of TDM_DEMUX_DBG is terminal TST_D2A_OUT: ELECTRICAL; signal RCVR_BUS: STD_LOGIC_VECTOR(0 to 11); signal \$BUF_RCVR_BUS_1_10_Port\: std_logic_vector(1 to 10); component BUF generic( DELAY : TIME:=0 NS ); port( signal INPUT : IN STD_LOGIC; signal OUTPUT : OUT STD_LOGIC ); end component BUF; component D2A_NBIT generic( HIGH_BIT : INTEGER:=9; LOW_BIT : INTEGER:=0; VMAX : REAL:=5.0; VMIN : REAL:=0.0 ); port( signal BUS_IN : IN STD_LOGIC_VECTOR(0 to 9); signal LATCH : IN STD_LOGIC; terminal ANA_OUT : ELECTRICAL ); end component D2A_NBIT; component PARITY_DET port( signal BUS_IN_0_11_Port : IN STD_LOGIC_VECTOR(0 to 11); signal OE : IN STD_LOGIC; signal PAR_BIT : OUT STD_LOGIC ); end component PARITY_DET; component FRAME_DET port( signal BUS_IN : IN STD_LOGIC_VECTOR(0 to 11); signal CLK : IN STD_LOGIC; signal FRM_BIT : OUT STD_LOGIC ); end component FRAME_DET; component S2P_SHIFT_REG port( signal CLK : IN STD_LOGIC; signal LOAD_EN : IN STD_LOGIC; signal PAR_OUT : OUT STD_LOGIC_VECTOR(0 to 11); signal RESET : IN STD_LOGIC; signal SER_IN : IN STD_LOGIC ); end component S2P_SHIFT_REG; for D2A1: D2A_NBIT use entity WORK.D2A_NBIT; for PAR_DET1: PARITY_DET use entity WORK.PARITY_DET(ARCH_PARITY_DET); for S2P_SHIFT_REG1: S2P_SHIFT_REG use entity WORK.S2P_SHIFT_REG; for FRM_DET1: FRAME_DET use entity WORK.FRAME_DET; for BUF1: BUF use entity EDULIB.BUF; begin RCVR_BUS_1_10_Port <= \$BUF_RCVR_BUS_1_10_Port\; D2A1 : D2A_NBIT generic map ( HIGH_BIT => 10, LOW_BIT => 1, VMAX => 4.8 ) port map ( BUS_IN(0) => \$BUF_RCVR_BUS_1_10_Port\(1), BUS_IN(1) => \$BUF_RCVR_BUS_1_10_Port\(2), BUS_IN(2) => \$BUF_RCVR_BUS_1_10_Port\(3), BUS_IN(3) => \$BUF_RCVR_BUS_1_10_Port\(4), BUS_IN(4) => \$BUF_RCVR_BUS_1_10_Port\(5), BUS_IN(5) => \$BUF_RCVR_BUS_1_10_Port\(6), BUS_IN(6) => \$BUF_RCVR_BUS_1_10_Port\(7), BUS_IN(7) => \$BUF_RCVR_BUS_1_10_Port\(8), BUS_IN(8) => \$BUF_RCVR_BUS_1_10_Port\(9), BUS_IN(9) => \$BUF_RCVR_BUS_1_10_Port\(10), LATCH => DA_LATCH, ANA_OUT => TST_D2A_OUT ); PAR_DET1 : PARITY_DET port map ( BUS_IN_0_11_Port(0) => RCVR_BUS(0), BUS_IN_0_11_Port(1) => \$BUF_RCVR_BUS_1_10_Port\(1), BUS_IN_0_11_Port(2) => \$BUF_RCVR_BUS_1_10_Port\(2), BUS_IN_0_11_Port(3) => \$BUF_RCVR_BUS_1_10_Port\(3), BUS_IN_0_11_Port(4) => \$BUF_RCVR_BUS_1_10_Port\(4), BUS_IN_0_11_Port(5) => \$BUF_RCVR_BUS_1_10_Port\(5), BUS_IN_0_11_Port(6) => \$BUF_RCVR_BUS_1_10_Port\(6), BUS_IN_0_11_Port(7) => \$BUF_RCVR_BUS_1_10_Port\(7), BUS_IN_0_11_Port(8) => \$BUF_RCVR_BUS_1_10_Port\(8), BUS_IN_0_11_Port(9) => \$BUF_RCVR_BUS_1_10_Port\(9), BUS_IN_0_11_Port(10) => \$BUF_RCVR_BUS_1_10_Port\(10), BUS_IN_0_11_Port(11) => RCVR_BUS(11), OE => PAR_OE, PAR_BIT => PAR_DET ); S2P_SHIFT_REG1 : S2P_SHIFT_REG port map ( CLK => CLK_6K, LOAD_EN => S2P_EN, PAR_OUT(0) => RCVR_BUS(0), PAR_OUT(1) => \$BUF_RCVR_BUS_1_10_Port\(1), PAR_OUT(2) => \$BUF_RCVR_BUS_1_10_Port\(2), PAR_OUT(3) => \$BUF_RCVR_BUS_1_10_Port\(3), PAR_OUT(4) => \$BUF_RCVR_BUS_1_10_Port\(4), PAR_OUT(5) => \$BUF_RCVR_BUS_1_10_Port\(5), PAR_OUT(6) => \$BUF_RCVR_BUS_1_10_Port\(6), PAR_OUT(7) => \$BUF_RCVR_BUS_1_10_Port\(7), PAR_OUT(8) => \$BUF_RCVR_BUS_1_10_Port\(8), PAR_OUT(9) => \$BUF_RCVR_BUS_1_10_Port\(9), PAR_OUT(10) => \$BUF_RCVR_BUS_1_10_Port\(10), PAR_OUT(11) => RCVR_BUS(11), RESET => S2P_RST, SER_IN => TDM_IN ); FRM_DET1 : FRAME_DET port map ( BUS_IN(0) => RCVR_BUS(0), BUS_IN(1) => \$BUF_RCVR_BUS_1_10_Port\(1), BUS_IN(2) => \$BUF_RCVR_BUS_1_10_Port\(2), BUS_IN(3) => \$BUF_RCVR_BUS_1_10_Port\(3), BUS_IN(4) => \$BUF_RCVR_BUS_1_10_Port\(4), BUS_IN(5) => \$BUF_RCVR_BUS_1_10_Port\(5), BUS_IN(6) => \$BUF_RCVR_BUS_1_10_Port\(6), BUS_IN(7) => \$BUF_RCVR_BUS_1_10_Port\(7), BUS_IN(8) => \$BUF_RCVR_BUS_1_10_Port\(8), BUS_IN(9) => \$BUF_RCVR_BUS_1_10_Port\(9), BUS_IN(10) => \$BUF_RCVR_BUS_1_10_Port\(10), BUS_IN(11) => RCVR_BUS(11), CLK => CLK_6K, FRM_BIT => FRM_DET ); BUF1 : BUF port map ( INPUT => RCVR_BUS(0), OUTPUT => START_BIT ); end architecture arch_TDM_DEMUX_DBG; -- -- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\Digital/clock_en.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : clock_en.vhd -- Author : Mentor Graphics -- Created : 2003/04/21 -- Last update: 2003/04/23 ------------------------------------------------------------------------------- -- Description: Digital clock with 50% duty cycle and enable ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2003/04/21 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity clock_en is generic ( period : time); -- Clock period port ( enable : in std_logic; clk_out : out std_logic); end entity clock_en; architecture ideal of clock_en is begin CreateClock : process begin if enable = '1' then clk_out <= '0'; wait for period/2; clk_out <= '1'; wait for period/2; else clk_out <= '0'; wait for period/2; end if; end process CreateClock; end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------ -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\genhdl\airplane_hcl\decode_pw.vhd -- genhdl\airplane_hcl/decode_pw.vhd -- Generated by SystemVision netlister 1.0 build 2003.325.1 -- File created Sat Nov 22 14:06:20 2003 library edulib; library ieee; library mgc_ams; use ieee.electrical_systems.all; use ieee.fluidic_systems.all; use ieee.mechanical_systems.all; use ieee.radiant_systems.all; use ieee.std_logic_1164.all; use ieee.thermal_systems.all; use mgc_ams.conversion.all; use work.all; entity DECODE_PW is port( signal BIT_STREAM_IN : IN STD_LOGIC; terminal CH1_PW : ELECTRICAL; terminal CH2_PW : ELECTRICAL ); end entity DECODE_PW; architecture arch_DECODE_PW of DECODE_PW is signal XSIG010266: STD_LOGIC; signal XSIG010267: STD_LOGIC; signal XSIG010268: STD_LOGIC; signal CNT2_EN: STD_LOGIC; signal CNT1_EN: STD_LOGIC; signal CNT1_CLK: STD_LOGIC; signal CNT2_CLK: STD_LOGIC; signal CLK_50: STD_LOGIC; signal \$1N81\: STD_LOGIC; signal CMP_BUS: STD_LOGIC_VECTOR(0 to 11); signal PAR_DET: STD_LOGIC; signal CNT2_LOAD: STD_LOGIC; signal CNT1_LOAD: STD_LOGIC; signal CLK_100K: STD_LOGIC; signal CLK1_RST: STD_LOGIC; signal TC1: STD_LOGIC; signal START_BIT: STD_LOGIC; signal FRM_DET: STD_LOGIC; signal CLK2_RST: STD_LOGIC; signal CLK2_EN: STD_LOGIC; signal TC2: STD_LOGIC; signal CLK_6K: STD_LOGIC; signal CLK1_EN: STD_LOGIC; component SM_CNT_RCVR port( signal CLK_100K : IN STD_LOGIC; signal CLK_50 : IN STD_LOGIC; signal CLK_6K : IN STD_LOGIC; signal CNT1_EN : OUT STD_LOGIC; signal CNT1_LOAD : OUT STD_LOGIC; signal CNT2_EN : OUT STD_LOGIC; signal CNT2_LOAD : OUT STD_LOGIC; signal DA_LATCH : OUT STD_LOGIC; signal FRM_DET : IN STD_LOGIC; signal PAR_DET : IN STD_LOGIC; signal PAR_OE : OUT STD_LOGIC; signal S2P_EN : OUT STD_LOGIC; signal S2P_RST : OUT STD_LOGIC; signal START_PULSE : IN STD_LOGIC ); end component SM_CNT_RCVR; component CLOCK_EN generic( PERIOD : TIME ); port( signal CLK_OUT : OUT STD_LOGIC; signal ENABLE : IN STD_LOGIC ); end component CLOCK_EN; component TDM_DEMUX_DBG port( signal CLK_6K : IN STD_LOGIC; signal DA_LATCH : IN STD_LOGIC; signal FRM_DET : OUT STD_LOGIC; signal PAR_DET : OUT STD_LOGIC; signal PAR_OE : IN STD_LOGIC; signal RCVR_BUS_1_10_Port : OUT STD_LOGIC_VECTOR(1 to 10); signal S2P_EN : IN STD_LOGIC; signal S2P_RST : IN STD_LOGIC; signal START_BIT : OUT STD_LOGIC; signal TDM_IN : IN STD_LOGIC ); end component TDM_DEMUX_DBG; component COUNTER_PRELOAD generic( NBITS : INTEGER:=12 ); port( signal DATA_IN : IN STD_LOGIC_VECTOR(0 to 11); signal CLK : IN STD_LOGIC; signal LOAD : IN STD_LOGIC; signal CNT_EN : IN STD_LOGIC; signal TC : OUT STD_LOGIC ); end component COUNTER_PRELOAD; component INVERTER generic( DELAY : TIME:=0NS ); port( signal INPUT : IN STD_LOGIC; signal OUTPUT : OUT STD_LOGIC ); end component INVERTER; component LEVEL_SET generic( LOGIC_VAL : STD_LOGIC:='1' ); port( signal LEVEL : OUT STD_LOGIC ); end component LEVEL_SET; component RC_CLK port( signal CLK_100K : OUT STD_LOGIC; signal CLK_50 : OUT STD_LOGIC; signal CLK_6K : OUT STD_LOGIC ); end component RC_CLK; component SR_FF port( signal S : IN STD_LOGIC; signal R : IN STD_LOGIC; signal Q : OUT STD_LOGIC ); end component SR_FF; component D2A_BIT generic( T_RAMP : REAL:=1.0E-9; VHIGH : VOLTAGE:=5.0; VLOW : VOLTAGE:=0.0 ); port( signal D : IN STD_LOGIC; terminal A : ELECTRICAL ); end component D2A_BIT; for SET0: LEVEL_SET use entity WORK.LEVEL_SET; for XCMP176: INVERTER use entity WORK.INVERTER; for CNTR1: COUNTER_PRELOAD use entity WORK.COUNTER_PRELOAD; for DA2: D2A_BIT use entity EDULIB.D2A_BIT; for INV2: INVERTER use entity WORK.INVERTER; for RC_CLK2: RC_CLK use entity WORK.RC_CLK(ARCH_RC_CLK); for SET1: LEVEL_SET use entity WORK.LEVEL_SET; for DA1: D2A_BIT use entity EDULIB.D2A_BIT; for SR_FF2: SR_FF use entity WORK.SR_FF; for STATE_MACHINE2: SM_CNT_RCVR use entity WORK.SM_CNT_RCVR(ARCH_SM_CNT_RCVR); for TDM_DEMUX_DBG2: TDM_DEMUX_DBG use entity WORK.TDM_DEMUX_DBG(ARCH_TDM_DEMUX_DBG); for CNTR2: COUNTER_PRELOAD use entity WORK.COUNTER_PRELOAD; for CLK_1M2: CLOCK_EN use entity EDULIB.CLOCK_EN; for CLK_1M1: CLOCK_EN use entity EDULIB.CLOCK_EN(IDEAL); for SR_FF1: SR_FF use entity WORK.SR_FF; begin SET0 : LEVEL_SET generic map ( LOGIC_VAL => '0' ) port map ( LEVEL => CMP_BUS(11) ); XCMP176 : INVERTER port map ( INPUT => TC1, OUTPUT => CLK1_RST ); CNTR1 : COUNTER_PRELOAD port map ( DATA_IN(0) => CMP_BUS(0), DATA_IN(1) => CMP_BUS(1), DATA_IN(2) => CMP_BUS(2), DATA_IN(3) => CMP_BUS(3), DATA_IN(4) => CMP_BUS(4), DATA_IN(5) => CMP_BUS(5), DATA_IN(6) => CMP_BUS(6), DATA_IN(7) => CMP_BUS(7), DATA_IN(8) => CMP_BUS(8), DATA_IN(9) => CMP_BUS(9), DATA_IN(10) => CMP_BUS(10), DATA_IN(11) => CMP_BUS(11), CLK => CNT1_CLK, LOAD => CNT1_LOAD, CNT_EN => CLK1_EN, TC => TC1 ); DA2 : D2A_BIT port map ( D => TC2, A => CH2_PW ); INV2 : INVERTER port map ( INPUT => TC2, OUTPUT => CLK2_RST ); RC_CLK2 : RC_CLK port map ( CLK_100K => CLK_100K, CLK_50 => CLK_50, CLK_6K => CLK_6K ); SET1 : LEVEL_SET generic map ( LOGIC_VAL => '1' ) port map ( LEVEL => CMP_BUS(10) ); DA1 : D2A_BIT port map ( D => TC1, A => CH1_PW ); SR_FF2 : SR_FF port map ( S => CNT2_EN, R => CLK2_RST, Q => CLK2_EN ); STATE_MACHINE2 : SM_CNT_RCVR port map ( CLK_100K => CLK_100K, CLK_50 => CLK_50, CLK_6K => CLK_6K, CNT1_EN => CNT1_EN, CNT1_LOAD => CNT1_LOAD, CNT2_EN => CNT2_EN, CNT2_LOAD => CNT2_LOAD, DA_LATCH => XSIG010268, FRM_DET => FRM_DET, PAR_DET => PAR_DET, PAR_OE => \$1N81\, S2P_EN => XSIG010266, S2P_RST => XSIG010267, START_PULSE => START_BIT ); TDM_DEMUX_DBG2 : TDM_DEMUX_DBG port map ( CLK_6K => CLK_6K, DA_LATCH => XSIG010268, FRM_DET => FRM_DET, PAR_DET => PAR_DET, PAR_OE => \$1N81\, RCVR_BUS_1_10_Port(1) => CMP_BUS(0), RCVR_BUS_1_10_Port(2) => CMP_BUS(1), RCVR_BUS_1_10_Port(3) => CMP_BUS(2), RCVR_BUS_1_10_Port(4) => CMP_BUS(3), RCVR_BUS_1_10_Port(5) => CMP_BUS(4), RCVR_BUS_1_10_Port(6) => CMP_BUS(5), RCVR_BUS_1_10_Port(7) => CMP_BUS(6), RCVR_BUS_1_10_Port(8) => CMP_BUS(7), RCVR_BUS_1_10_Port(9) => CMP_BUS(8), RCVR_BUS_1_10_Port(10) => CMP_BUS(9), S2P_EN => XSIG010266, S2P_RST => XSIG010267, START_BIT => START_BIT, TDM_IN => BIT_STREAM_IN ); CNTR2 : COUNTER_PRELOAD port map ( DATA_IN(0) => CMP_BUS(0), DATA_IN(1) => CMP_BUS(1), DATA_IN(2) => CMP_BUS(2), DATA_IN(3) => CMP_BUS(3), DATA_IN(4) => CMP_BUS(4), DATA_IN(5) => CMP_BUS(5), DATA_IN(6) => CMP_BUS(6), DATA_IN(7) => CMP_BUS(7), DATA_IN(8) => CMP_BUS(8), DATA_IN(9) => CMP_BUS(9), DATA_IN(10) => CMP_BUS(10), DATA_IN(11) => CMP_BUS(11), CLK => CNT2_CLK, LOAD => CNT2_LOAD, CNT_EN => CLK2_EN, TC => TC2 ); CLK_1M2 : CLOCK_EN generic map ( PERIOD => 1 US ) port map ( CLK_OUT => CNT2_CLK, ENABLE => CLK2_EN ); CLK_1M1 : CLOCK_EN generic map ( PERIOD => 1 US ) port map ( CLK_OUT => CNT1_CLK, ENABLE => CLK1_EN ); SR_FF1 : SR_FF port map ( S => CNT1_EN, R => CLK1_RST, Q => CLK1_EN ); end architecture arch_DECODE_PW; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\d2a_12_bit.vhd library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE; use IEEE.electrical_systems.all; ENTITY d2a_12_bit IS GENERIC ( vmax : real := 5.0; -- High output vmin : real := 0.0; -- Low output high_bit : integer := 9; -- High end of bit range for D/A low_bit : integer := 0); -- Low end of bit range for D/A PORT ( SIGNAL bus_in : IN STD_LOGIC_VECTOR(low_bit to high_bit); -- variable width vector input SIGNAL latch : IN STD_LOGIC; TERMINAL ana_out : electrical); -- analog output END ENTITY d2a_12_bit ; ARCHITECTURE behavioral OF d2a_12_bit IS SIGNAL sout : real := 0.0; QUANTITY vout across iout through ana_out TO electrical_ref; BEGIN -- ARCHITECTURE behavioral proc : PROCESS VARIABLE v_sum : real; -- Sum of voltage contribution from each bit VARIABLE delt_v : real; -- Represents the voltage value of each bit BEGIN WAIT UNTIL (latch'event and latch = '1'); -- Begin when latch goes high v_sum := vmin; delt_v := vmax - vmin; FOR i IN high_bit DOWNTO low_bit LOOP -- Perform the conversions delt_v := delt_v / 2.0; IF bus_in(i) = '1' OR bus_in(i) = 'H' THEN v_sum := v_sum + delt_v; END IF; END LOOP; sout <= v_sum; END PROCESS; vout == sout'ramp(100.0E-9); -- Ensure continuous transition between levels END ARCHITECTURE behavioral; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\or2.vhd -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Two input OR gate LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY or2 IS GENERIC ( delay : time := 0 ns); -- Delay time PORT ( in1, in2 : IN std_logic; output : OUT std_logic); END ENTITY or2; ARCHITECTURE ideal OF or2 IS BEGIN output <= in1 OR in2 AFTER delay; END ARCHITECTURE ideal; -- -- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\MixedSignal/a2d_bit.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : a2d_bit.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2003-05-13 ------------------------------------------------------------------------------- -- Description: Ideal one bit A/D converter ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- library IEEE; use IEEE.math_real.all; use IEEE.std_logic_1164.all; use IEEE.electrical_systems.all; entity a2d_bit is generic ( thres : voltage := 2.5); -- Threshold to determine logic output port ( terminal a : electrical; -- analog input signal d : out std_logic); -- digital (std_logic) output end entity a2d_bit; ------------------------------------------------------------------------------- -- Ideal architecture -- Uses 'above operator to detect threshold crossing ------------------------------------------------------------------------------- architecture ideal of a2d_bit is quantity vin across a; begin -- purpose: Detect threshold crossing and assign event on output (d) -- type : combinational -- inputs : vin'above(thres) -- outputs: pulse_signal process (vin'above(thres)) is begin -- PROCESS if vin'above(thres) then d <= '1'; else d <= '0'; end if; end process; end ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\d_latch_n_edge_rst.vhd -- D Flip Flop with reset (negative edge triggered) LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY d_latch_n_edge_rst IS GENERIC ( delay : time := 0 ns); -- Delay time PORT ( data, clk : IN std_logic; q : OUT std_logic := '0'; qn : OUT std_logic := '1'; rst : IN std_logic := '0'); -- reset END ENTITY d_latch_n_edge_rst ; ARCHITECTURE behav OF d_latch_n_edge_rst IS BEGIN data_in : PROCESS(clk, rst) IS BEGIN IF clk = '0' AND clk'event AND rst /= '1' THEN q <= data AFTER delay; qn <= NOT data AFTER delay; ELSIF rst = '1' THEN q <= '0'; qn <= '1'; END IF; END PROCESS data_in; -- End of process data_in END ARCHITECTURE behav; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\genhdl\airplane_hcl\counter_12.vhd -- genhdl\airplane_hcl/counter_12.vhd -- Generated by SystemVision netlister 1.0 build 2003.325.1 -- File created Sat Nov 22 14:06:20 2003 library edulib; library ieee; library mgc_ams; use ieee.electrical_systems.all; use ieee.fluidic_systems.all; use ieee.mechanical_systems.all; use ieee.radiant_systems.all; use ieee.std_logic_1164.all; use ieee.thermal_systems.all; use mgc_ams.conversion.all; use work.all; entity COUNTER_12 is port( signal CLK : IN STD_LOGIC; signal CNT_0_11_Port : OUT STD_LOGIC_VECTOR(0 to 11); signal ENABLE : IN STD_LOGIC; signal RESET : IN STD_LOGIC ); end entity COUNTER_12; architecture arch_COUNTER_12 of COUNTER_12 is signal XSIG010132: STD_LOGIC; signal XSIG010078: STD_LOGIC; signal XSIG010101: STD_LOGIC; signal XSIG010102: STD_LOGIC; signal XSIG010103: STD_LOGIC; signal XSIG010115: STD_LOGIC; signal XSIG010104: STD_LOGIC; signal XSIG010116: STD_LOGIC; signal XSIG010117: STD_LOGIC; signal XSIG010081: STD_LOGIC; signal XSIG010083: STD_LOGIC; signal \$BUF_CNT_0_11_Port\: std_logic_vector(0 to 11); signal XSIG010085: STD_LOGIC; signal XSIG010087: STD_LOGIC; component AND2 generic( DELAY : TIME:=0NS ); port( signal IN1 : IN STD_LOGIC; signal IN2 : IN STD_LOGIC; signal OUTPUT : OUT STD_LOGIC ); end component AND2; component D_LATCH_N_EDGE_RST generic( DELAY : TIME:=0NS ); port( signal DATA : IN STD_LOGIC; signal CLK : IN STD_LOGIC; signal Q : OUT STD_LOGIC; signal QN : OUT STD_LOGIC; signal RST : IN STD_LOGIC ); end component D_LATCH_N_EDGE_RST; for XCMP104: D_LATCH_N_EDGE_RST use entity WORK.D_LATCH_N_EDGE_RST; for XCMP95: D_LATCH_N_EDGE_RST use entity WORK.D_LATCH_N_EDGE_RST; for XCMP94: D_LATCH_N_EDGE_RST use entity WORK.D_LATCH_N_EDGE_RST; for XCMP93: D_LATCH_N_EDGE_RST use entity WORK.D_LATCH_N_EDGE_RST; for XCMP92: AND2 use entity WORK.AND2; for XCMP103: D_LATCH_N_EDGE_RST use entity WORK.D_LATCH_N_EDGE_RST; for XCMP102: D_LATCH_N_EDGE_RST use entity WORK.D_LATCH_N_EDGE_RST; for XCMP101: D_LATCH_N_EDGE_RST use entity WORK.D_LATCH_N_EDGE_RST; for XCMP100: D_LATCH_N_EDGE_RST use entity WORK.D_LATCH_N_EDGE_RST; for XCMP99: D_LATCH_N_EDGE_RST use entity WORK.D_LATCH_N_EDGE_RST; for XCMP98: D_LATCH_N_EDGE_RST use entity WORK.D_LATCH_N_EDGE_RST; for XCMP97: D_LATCH_N_EDGE_RST use entity WORK.D_LATCH_N_EDGE_RST; for XCMP96: D_LATCH_N_EDGE_RST use entity WORK.D_LATCH_N_EDGE_RST; begin CNT_0_11_Port <= \$BUF_CNT_0_11_Port\; XCMP104 : D_LATCH_N_EDGE_RST port map ( DATA => XSIG010117, CLK => \$BUF_CNT_0_11_Port\(10), Q => \$BUF_CNT_0_11_Port\(11), QN => XSIG010117, RST => RESET ); XCMP95 : D_LATCH_N_EDGE_RST port map ( DATA => XSIG010083, CLK => \$BUF_CNT_0_11_Port\(1), Q => \$BUF_CNT_0_11_Port\(2), QN => XSIG010083, RST => RESET ); XCMP94 : D_LATCH_N_EDGE_RST port map ( DATA => XSIG010081, CLK => \$BUF_CNT_0_11_Port\(0), Q => \$BUF_CNT_0_11_Port\(1), QN => XSIG010081, RST => RESET ); XCMP93 : D_LATCH_N_EDGE_RST port map ( DATA => XSIG010078, CLK => XSIG010132, Q => \$BUF_CNT_0_11_Port\(0), QN => XSIG010078, RST => RESET ); XCMP92 : AND2 port map ( IN1 => CLK, IN2 => ENABLE, OUTPUT => XSIG010132 ); XCMP103 : D_LATCH_N_EDGE_RST port map ( DATA => XSIG010116, CLK => \$BUF_CNT_0_11_Port\(9), Q => \$BUF_CNT_0_11_Port\(10), QN => XSIG010116, RST => RESET ); XCMP102 : D_LATCH_N_EDGE_RST port map ( DATA => XSIG010115, CLK => \$BUF_CNT_0_11_Port\(8), Q => \$BUF_CNT_0_11_Port\(9), QN => XSIG010115, RST => RESET ); XCMP101 : D_LATCH_N_EDGE_RST port map ( DATA => XSIG010104, CLK => \$BUF_CNT_0_11_Port\(7), Q => \$BUF_CNT_0_11_Port\(8), QN => XSIG010104, RST => RESET ); XCMP100 : D_LATCH_N_EDGE_RST port map ( DATA => XSIG010103, CLK => \$BUF_CNT_0_11_Port\(6), Q => \$BUF_CNT_0_11_Port\(7), QN => XSIG010103, RST => RESET ); XCMP99 : D_LATCH_N_EDGE_RST port map ( DATA => XSIG010102, CLK => \$BUF_CNT_0_11_Port\(5), Q => \$BUF_CNT_0_11_Port\(6), QN => XSIG010102, RST => RESET ); XCMP98 : D_LATCH_N_EDGE_RST port map ( DATA => XSIG010101, CLK => \$BUF_CNT_0_11_Port\(4), Q => \$BUF_CNT_0_11_Port\(5), QN => XSIG010101, RST => RESET ); XCMP97 : D_LATCH_N_EDGE_RST port map ( DATA => XSIG010087, CLK => \$BUF_CNT_0_11_Port\(3), Q => \$BUF_CNT_0_11_Port\(4), QN => XSIG010087, RST => RESET ); XCMP96 : D_LATCH_N_EDGE_RST port map ( DATA => XSIG010085, CLK => \$BUF_CNT_0_11_Port\(2), Q => \$BUF_CNT_0_11_Port\(3), QN => XSIG010085, RST => RESET ); end architecture arch_COUNTER_12; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\genhdl\airplane_hcl\pw2ana.vhd -- genhdl\airplane_hcl/pw2ana.vhd -- Generated by SystemVision netlister 1.0 build 2003.325.1 -- File created Sat Nov 22 14:06:20 2003 library edulib; library ieee; library mgc_ams; use ieee.electrical_systems.all; use ieee.fluidic_systems.all; use ieee.mechanical_systems.all; use ieee.radiant_systems.all; use ieee.std_logic_1164.all; use ieee.thermal_systems.all; use mgc_ams.conversion.all; use work.all; entity PW2ANA is port( terminal ANA_OUT : ELECTRICAL; terminal PW_IN : ELECTRICAL ); end entity PW2ANA; architecture arch_PW2ANA of PW2ANA is signal XSIG010022: STD_LOGIC; signal XSIG010013: STD_LOGIC; signal XSIG010019: STD_LOGIC; signal BUS_SERVO: STD_LOGIC_VECTOR(0 to 11); signal XSIG010020: STD_LOGIC; signal XSIG010021: STD_LOGIC; signal \$1N24\: STD_LOGIC; component CLOCK_EN generic( PERIOD : TIME ); port( signal CLK_OUT : OUT STD_LOGIC; signal ENABLE : IN STD_LOGIC ); end component CLOCK_EN; component COUNTER_12 port( signal CLK : IN STD_LOGIC; signal CNT_0_11_Port : OUT STD_LOGIC_VECTOR(0 to 11); signal ENABLE : IN STD_LOGIC; signal RESET : IN STD_LOGIC ); end component COUNTER_12; component INVERTER generic( DELAY : TIME:=0NS ); port( signal INPUT : IN STD_LOGIC; signal OUTPUT : OUT STD_LOGIC ); end component INVERTER; component A2D_BIT generic( THRES : REAL:=2.5 ); port( terminal A : ELECTRICAL; signal D : OUT STD_LOGIC ); end component A2D_BIT; component OR2 generic( DELAY : TIME:=0NS ); port( signal IN1 : IN STD_LOGIC; signal IN2 : IN STD_LOGIC; signal OUTPUT : OUT STD_LOGIC ); end component OR2; component D2A_12_BIT generic( HIGH_BIT : INTEGER:=9; LOW_BIT : INTEGER:=0; VMAX : REAL:=5.0; VMIN : REAL:=0.0 ); port( signal BUS_IN : IN STD_LOGIC_VECTOR(0 to 11); signal LATCH : IN STD_LOGIC; terminal ANA_OUT : ELECTRICAL ); end component D2A_12_BIT; for DA1: D2A_12_BIT use entity WORK.D2A_12_BIT; for OR_RUDDER: OR2 use entity WORK.OR2; for INV2: INVERTER use entity WORK.INVERTER; for INV3: INVERTER use entity WORK.INVERTER; for INV1: INVERTER use entity WORK.INVERTER; for CLK_EN_RUDDER: CLOCK_EN use entity EDULIB.CLOCK_EN(IDEAL); for AD1: A2D_BIT use entity EDULIB.A2D_BIT; for COUNTER_RUDDER: COUNTER_12 use entity WORK.COUNTER_12(ARCH_COUNTER_12); begin DA1 : D2A_12_BIT generic map ( HIGH_BIT => 9, LOW_BIT => 0, VMAX => 4.8 ) port map ( BUS_IN(0) => BUS_SERVO(0), BUS_IN(1) => BUS_SERVO(1), BUS_IN(2) => BUS_SERVO(2), BUS_IN(3) => BUS_SERVO(3), BUS_IN(4) => BUS_SERVO(4), BUS_IN(5) => BUS_SERVO(5), BUS_IN(6) => BUS_SERVO(6), BUS_IN(7) => BUS_SERVO(7), BUS_IN(8) => BUS_SERVO(8), BUS_IN(9) => BUS_SERVO(9), BUS_IN(10) => BUS_SERVO(10), BUS_IN(11) => BUS_SERVO(11), LATCH => XSIG010013, ANA_OUT => ANA_OUT ); OR_RUDDER : OR2 port map ( IN1 => XSIG010022, IN2 => XSIG010019, OUTPUT => XSIG010020 ); INV2 : INVERTER generic map ( DELAY => 2US ) port map ( INPUT => XSIG010022, OUTPUT => XSIG010019 ); INV3 : INVERTER generic map ( DELAY => 2US ) port map ( INPUT => XSIG010020, OUTPUT => XSIG010021 ); INV1 : INVERTER generic map ( DELAY => 2US ) port map ( INPUT => XSIG010022, OUTPUT => XSIG010013 ); CLK_EN_RUDDER : CLOCK_EN generic map ( PERIOD => 1 US ) port map ( CLK_OUT => \$1N24\, ENABLE => XSIG010022 ); AD1 : A2D_BIT port map ( A => PW_IN, D => XSIG010022 ); COUNTER_RUDDER : COUNTER_12 port map ( CLK => \$1N24\, CNT_0_11_Port(0) => BUS_SERVO(0), CNT_0_11_Port(1) => BUS_SERVO(1), CNT_0_11_Port(2) => BUS_SERVO(2), CNT_0_11_Port(3) => BUS_SERVO(3), CNT_0_11_Port(4) => BUS_SERVO(4), CNT_0_11_Port(5) => BUS_SERVO(5), CNT_0_11_Port(6) => BUS_SERVO(6), CNT_0_11_Port(7) => BUS_SERVO(7), CNT_0_11_Port(8) => BUS_SERVO(8), CNT_0_11_Port(9) => BUS_SERVO(9), CNT_0_11_Port(10) => BUS_SERVO(10), CNT_0_11_Port(11) => BUS_SERVO(11), ENABLE => XSIG010022, RESET => XSIG010021 ); end architecture arch_PW2ANA; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\lpf_2_e.vhd ------------------------------------------------------------------------------- -- Second Order Lowpass filter -- -- Transfer Function: -- -- w1*w2 -- H(s) = k * ---------------- -- (s + w1)(s + w2) -- -- DC Gain = k ------------------------------------------------------------------------------- library IEEE; use IEEE.electrical_systems.all; use ieee.math_real.all; entity lpf_2_e is generic ( k: real := 1.0; -- Gain multiplier f1: real := 10.0; -- First break frequency (pole) f2: real := 100.0); -- Second break frequency (pole) port ( terminal input: electrical; terminal output: electrical); end entity lpf_2_e; architecture simple of lpf_2_e is QUANTITY vin ACROSS input TO ELECTRICAL_REF; QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF; quantity vin_temp : real; constant w1 : real := f1*math_2_pi; constant w2 : real := f2*math_2_pi; -- constant num : real := k; constant num : real_vector := (0 => w1*w2*k); -- 0=> is needed to give -- index when only a single -- element is used. constant den : real_vector := (w1*w2, w1+w2, 1.0); begin vin_temp == vin; -- intermediate variable (vin) req'd for now vout == vin_temp'ltf(num, den); end architecture simple; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\switch_dig_2in.vhd -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Simple Digital-Controlled Two-position Switch Model -- Switch position 1 ('0') or switch position 2 ('1') LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; use IEEE.std_logic_arith.all; use IEEE.math_real.all; -- Use proposed IEEE natures and packages LIBRARY IEEE; USE IEEE.electrical_systems.ALL; ENTITY switch_dig_2in is GENERIC (r_open : RESISTANCE := 1.0e6; -- Open switch resistance r_closed : RESISTANCE := 0.001; -- Closed switch resistance trans_time : real := 0.00001); -- Transition time to each position PORT (sw_state : in std_logic; -- Digital control input TERMINAL p_in1, p_in2, p_out : ELECTRICAL); -- Analog output END ENTITY switch_dig_2in; ARCHITECTURE ideal OF switch_dig_2in IS SIGNAL r_sig1 : RESISTANCE := r_closed; -- Variable to accept switch resistance SIGNAL r_sig2 : RESISTANCE := r_open; -- Variable to accept switch resistance QUANTITY v1 ACROSS i1 THROUGH p_in1 TO p_out; -- V & I for in1 to out QUANTITY v2 ACROSS i2 THROUGH p_in2 TO p_out; -- V & I for in2 to out QUANTITY r1 : RESISTANCE; -- Time-varying resistance for in1 to out QUANTITY r2 : RESISTANCE; -- Time-varying resistance for in2 to out BEGIN PROCESS (sw_state) -- Sensitivity to digital control input BEGIN IF (sw_state = '0') THEN -- Close sig1, open sig2 r_sig1 <= r_closed; r_sig2 <= r_open; ELSIF (sw_state = '1') THEN -- Open sig1, close sig2 r_sig1 <= r_open; r_sig2 <= r_closed; END IF; END PROCESS; r1 == r_sig1'ramp(trans_time, trans_time); -- Ensure resistance continuity r2 == r_sig2'ramp(trans_time, trans_time); -- Ensure resistance continuity v1 == r1*i1; -- Apply Ohm's law to in1 v2 == r2*i2; -- Apply Ohm's law to in2 END ARCHITECTURE ideal; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\state_mach1.vhd LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; LIBRARY IEEE_proposed; USE IEEE_proposed.electrical_systems.all; USE IEEE_proposed.mechanical_systems.all; USE IEEE_proposed.fluidic_systems.all; USE IEEE_proposed.thermal_systems.all; USE IEEE_proposed.radiant_systems.all; ENTITY state_mach1 IS PORT ( a2d_eoc : IN std_logic; clk_50 : IN std_logic; clk_100k : IN std_logic; clk_6k : IN std_logic; ser_done : IN std_logic; ch_sel : OUT std_logic; frm_gen : OUT std_logic; a2d_oe : OUT std_logic; a2d_start : OUT std_logic; p2s_oe : OUT std_logic; p2s_load : OUT std_logic; parity_oe : OUT std_logic; ser_cnt : OUT std_logic; p2s_clr : OUT std_logic); END state_mach1; ARCHITECTURE state_diagram OF state_mach1 IS ATTRIBUTE ENUM_TYPE_ENCODING: STRING; TYPE TYP_state_mach1_sm1 IS (V_begin, frm_rd, ser_oe, ch1, data_en, tdm_oe, ch2 , load, ad_ch2, delay); SIGNAL CS_state_mach1_sm1, NS_state_mach1_sm1 : TYP_state_mach1_sm1; SIGNAL FB_frm_gen : std_logic; SIGNAL FB_p2s_load : std_logic; SIGNAL FB_ch_sel : std_logic; BEGIN frm_gen <= FB_frm_gen ; p2s_load <= FB_p2s_load ; ch_sel <= FB_ch_sel ; sm1: PROCESS (CS_state_mach1_sm1, clk_50, FB_frm_gen, FB_p2s_load, ser_done, a2d_eoc, FB_ch_sel) BEGIN CASE CS_state_mach1_sm1 IS WHEN V_begin => FB_frm_gen <= ('1'); a2d_start <= ('0'); a2d_oe <= ('0'); FB_p2s_load <= ('0'); p2s_clr <= ('0'); p2s_oe <= ('0'); FB_ch_sel <= ('0'); parity_oe <= ('0'); ser_cnt <= ('0'); IF ((FB_frm_gen = '1')) THEN NS_state_mach1_sm1 <= frm_rd; ELSE NS_state_mach1_sm1 <= V_begin; END IF; WHEN frm_rd => FB_p2s_load <= ('1'); IF ((FB_p2s_load = '1')) THEN NS_state_mach1_sm1 <= ser_oe; ELSE NS_state_mach1_sm1 <= frm_rd; END IF; WHEN ser_oe => p2s_oe <= ('1'); FB_frm_gen <= ('0'); FB_p2s_load <= ('0'); ser_cnt <= ('1'); IF ((ser_done = '1')) THEN NS_state_mach1_sm1 <= ch1; ELSE NS_state_mach1_sm1 <= ser_oe; END IF; WHEN ch1 => p2s_oe <= ('0'); FB_ch_sel <= ('0'); a2d_start <= ('1'); ser_cnt <= ('0'); IF ((a2d_eoc = '1')) THEN NS_state_mach1_sm1 <= data_en; ELSE NS_state_mach1_sm1 <= ch1; END IF; WHEN data_en => a2d_start <= ('0'); a2d_oe <= ('1'); parity_oe <= ('1'); NS_state_mach1_sm1 <= load; WHEN tdm_oe => a2d_oe <= ('0'); parity_oe <= ('0'); p2s_oe <= ('1'); FB_p2s_load <= ('0'); ser_cnt <= ('1'); IF (((ser_done = '1') AND (FB_ch_sel = '0'))) THEN NS_state_mach1_sm1 <= ch2; ELSE NS_state_mach1_sm1 <= tdm_oe; END IF; WHEN ch2 => p2s_oe <= ('0'); ser_cnt <= ('0'); FB_ch_sel <= ('1'); NS_state_mach1_sm1 <= delay; WHEN load => FB_p2s_load <= ('1'); NS_state_mach1_sm1 <= tdm_oe; WHEN ad_ch2 => a2d_start <= ('1'); IF ((a2d_eoc = '1')) THEN NS_state_mach1_sm1 <= data_en; ELSE NS_state_mach1_sm1 <= ad_ch2; END IF; WHEN delay => NS_state_mach1_sm1 <= ad_ch2; END CASE; END PROCESS; sm1_CTL: PROCESS (clk_100k, clk_50) BEGIN IF (clk_100k'event AND clk_100k='1') THEN IF (clk_50= '1' ) THEN CS_state_mach1_sm1 <= V_begin; ELSE CS_state_mach1_sm1 <= NS_state_mach1_sm1; END IF; END IF; END PROCESS; END state_diagram; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\genhdl\airplane_hcl\sm_cnt.vhd -- genhdl\airplane_hcl/sm_cnt.vhd -- Generated by SystemVision netlister 1.0 build 2003.325.1 -- File created Sat Nov 22 14:06:20 2003 library edulib; library ieee; library mgc_ams; use ieee.electrical_systems.all; use ieee.fluidic_systems.all; use ieee.mechanical_systems.all; use ieee.radiant_systems.all; use ieee.std_logic_1164.all; use ieee.thermal_systems.all; use mgc_ams.conversion.all; use work.all; entity SM_CNT is port( signal A2D_EOC : IN STD_LOGIC; signal A2D_OE : OUT STD_LOGIC; signal A2D_START : OUT STD_LOGIC; signal CH_SEL : OUT STD_LOGIC; signal CLK_100K : IN STD_LOGIC; signal CLK_50 : IN STD_LOGIC; signal CLK_6K : IN STD_LOGIC; signal FRM_GEN : OUT STD_LOGIC; signal P2S_CLR : OUT STD_LOGIC; signal P2S_LOAD : OUT STD_LOGIC; signal P2S_OE : OUT STD_LOGIC; signal PARITY_OE : OUT STD_LOGIC ); end entity SM_CNT; architecture arch_SM_CNT of SM_CNT is signal SERIAL_CNT: STD_LOGIC; signal SER_DONE: STD_LOGIC; component STATE_MACH1 port( signal A2D_EOC : IN STD_LOGIC; signal A2D_OE : OUT STD_LOGIC; signal A2D_START : OUT STD_LOGIC; signal CH_SEL : OUT STD_LOGIC; signal CLK_100K : IN STD_LOGIC; signal CLK_50 : IN STD_LOGIC; signal CLK_6K : IN STD_LOGIC; signal FRM_GEN : OUT STD_LOGIC; signal P2S_CLR : OUT STD_LOGIC; signal P2S_LOAD : OUT STD_LOGIC; signal P2S_OE : OUT STD_LOGIC; signal PARITY_OE : OUT STD_LOGIC; signal SER_CNT : OUT STD_LOGIC; signal SER_DONE : IN STD_LOGIC ); end component STATE_MACH1; component BIT_CNT generic( COUNT : INTEGER ); port( signal BIT_IN : IN STD_LOGIC; signal CLK : IN STD_LOGIC; signal DLY_OUT : OUT STD_LOGIC ); end component BIT_CNT; for STATE_MACH16: STATE_MACH1 use entity WORK.STATE_MACH1; for BIT_CNT1: BIT_CNT use entity WORK.BIT_CNT; begin STATE_MACH16 : STATE_MACH1 port map ( A2D_EOC => A2D_EOC, A2D_OE => A2D_OE, A2D_START => A2D_START, CH_SEL => CH_SEL, CLK_100K => CLK_100K, CLK_50 => CLK_50, CLK_6K => CLK_6K, FRM_GEN => FRM_GEN, P2S_CLR => P2S_CLR, P2S_LOAD => P2S_LOAD, P2S_OE => P2S_OE, PARITY_OE => PARITY_OE, SER_CNT => SERIAL_CNT, SER_DONE => SER_DONE ); BIT_CNT1 : BIT_CNT generic map ( COUNT => 15 ) port map ( BIT_IN => SERIAL_CNT, CLK => CLK_6K, DLY_OUT => SER_DONE ); end architecture arch_SM_CNT; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\buffer_tri.vhd -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Simple Tri-state Buffer with delay time -- If OE = 1, output = input after delay -- If OE /= 1, output = Z after delay LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY buffer_tri IS GENERIC ( delay : time := 0 ns); -- Delay time PORT ( input : IN std_logic; OE : IN std_logic; output : OUT std_logic); END ENTITY buffer_tri; ARCHITECTURE ideal OF buffer_tri IS BEGIN oe_ctl: PROCESS BEGIN WAIT ON OE, input; IF OE = '1' THEN output <= input AFTER delay; ELSE output <= 'Z' AFTER delay; END IF; END PROCESS; END ARCHITECTURE ideal; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\level_set_tri.vhd -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- level_set_tri.vhd -- If OE = '1' set digital output "level" with parameter "logic_val" (default is 'Z') -- If OE = '0' set output to high impedance LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY level_set_tri IS GENERIC ( logic_val : std_logic := 'Z'); PORT ( OE : IN std_logic; level : OUT std_logic := 'Z'); END ENTITY level_set_tri; -- Simple architecture ARCHITECTURE ideal OF level_set_tri IS BEGIN oe_ctl: PROCESS BEGIN WAIT ON OE; IF OE = '1' THEN level <= logic_val; ELSE level <= 'Z'; END IF; END PROCESS; END ARCHITECTURE ideal; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\genhdl\airplane_hcl\parity_gen.vhd -- genhdl\airplane_hcl/parity_gen.vhd -- Generated by SystemVision netlister 1.0 build 2003.325.1 -- File created Sat Nov 22 14:06:20 2003 library edulib; library ieee; library mgc_ams; use ieee.electrical_systems.all; use ieee.fluidic_systems.all; use ieee.mechanical_systems.all; use ieee.radiant_systems.all; use ieee.std_logic_1164.all; use ieee.thermal_systems.all; use mgc_ams.conversion.all; use work.all; entity PARITY_GEN is port( signal OE : IN STD_LOGIC; signal PARITY_1_10_Port : IN STD_LOGIC_VECTOR(1 to 10); signal PARITY_OUT_0_11_Port : OUT STD_LOGIC_VECTOR(0 to 11) ); end entity PARITY_GEN; architecture arch_PARITY_GEN of PARITY_GEN is signal XSIG010002: STD_LOGIC; signal XSIG010003: STD_LOGIC; signal XSIG010004: STD_LOGIC; signal XSIG010005: STD_LOGIC; signal XSIG010006: STD_LOGIC; signal XSIG010007: STD_LOGIC; signal XSIG010008: STD_LOGIC; signal XSIG010009: STD_LOGIC; signal PAR_BIT_GEN: STD_LOGIC; component BUFFER_TRI generic( DELAY : TIME:=0NS ); port( signal INPUT : IN STD_LOGIC; signal OE : IN STD_LOGIC; signal OUTPUT : OUT STD_LOGIC ); end component BUFFER_TRI; component XOR2 generic( DELAY : TIME:=0NS ); port( signal IN1 : IN STD_LOGIC; signal IN2 : IN STD_LOGIC; signal OUTPUT : OUT STD_LOGIC ); end component XOR2; component LEVEL_SET_TRI generic( LOGIC_VAL : STD_LOGIC:='Z' ); port( signal OE : IN STD_LOGIC; signal LEVEL : OUT STD_LOGIC ); end component LEVEL_SET_TRI; for XCMP29: BUFFER_TRI use entity WORK.BUFFER_TRI; for XCMP28: BUFFER_TRI use entity WORK.BUFFER_TRI; for XCMP27: BUFFER_TRI use entity WORK.BUFFER_TRI; for XCMP26: BUFFER_TRI use entity WORK.BUFFER_TRI; for XCMP25: BUFFER_TRI use entity WORK.BUFFER_TRI; for XCMP24: BUFFER_TRI use entity WORK.BUFFER_TRI; for XCMP23: BUFFER_TRI use entity WORK.BUFFER_TRI; for XCMP22: BUFFER_TRI use entity WORK.BUFFER_TRI; for XCMP21: BUFFER_TRI use entity WORK.BUFFER_TRI; for XCMP20: BUFFER_TRI use entity WORK.BUFFER_TRI; for XCMP19: BUFFER_TRI use entity WORK.BUFFER_TRI; for XCMP18: LEVEL_SET_TRI use entity WORK.LEVEL_SET_TRI; for XCMP9: XOR2 use entity WORK.XOR2; for XCMP8: XOR2 use entity WORK.XOR2; for XCMP7: XOR2 use entity WORK.XOR2; for XCMP6: XOR2 use entity WORK.XOR2; for XCMP5: XOR2 use entity WORK.XOR2; for XCMP4: XOR2 use entity WORK.XOR2; for XCMP3: XOR2 use entity WORK.XOR2; for XCMP2: XOR2 use entity WORK.XOR2; for XCMP1: XOR2 use entity WORK.XOR2; begin XCMP29 : BUFFER_TRI port map ( INPUT => PAR_BIT_GEN, OE => OE, OUTPUT => PARITY_OUT_0_11_Port(0) ); XCMP28 : BUFFER_TRI port map ( INPUT => PARITY_1_10_Port(10), OE => OE, OUTPUT => PARITY_OUT_0_11_Port(10) ); XCMP27 : BUFFER_TRI port map ( INPUT => PARITY_1_10_Port(9), OE => OE, OUTPUT => PARITY_OUT_0_11_Port(9) ); XCMP26 : BUFFER_TRI port map ( INPUT => PARITY_1_10_Port(8), OE => OE, OUTPUT => PARITY_OUT_0_11_Port(8) ); XCMP25 : BUFFER_TRI port map ( INPUT => PARITY_1_10_Port(7), OE => OE, OUTPUT => PARITY_OUT_0_11_Port(7) ); XCMP24 : BUFFER_TRI port map ( INPUT => PARITY_1_10_Port(6), OE => OE, OUTPUT => PARITY_OUT_0_11_Port(6) ); XCMP23 : BUFFER_TRI port map ( INPUT => PARITY_1_10_Port(5), OE => OE, OUTPUT => PARITY_OUT_0_11_Port(5) ); XCMP22 : BUFFER_TRI port map ( INPUT => PARITY_1_10_Port(4), OE => OE, OUTPUT => PARITY_OUT_0_11_Port(4) ); XCMP21 : BUFFER_TRI port map ( INPUT => PARITY_1_10_Port(3), OE => OE, OUTPUT => PARITY_OUT_0_11_Port(3) ); XCMP20 : BUFFER_TRI port map ( INPUT => PARITY_1_10_Port(2), OE => OE, OUTPUT => PARITY_OUT_0_11_Port(2) ); XCMP19 : BUFFER_TRI port map ( INPUT => PARITY_1_10_Port(1), OE => OE, OUTPUT => PARITY_OUT_0_11_Port(1) ); XCMP18 : LEVEL_SET_TRI generic map ( LOGIC_VAL => '1' ) port map ( OE => OE, LEVEL => PARITY_OUT_0_11_Port(11) ); XCMP9 : XOR2 port map ( IN1 => XSIG010009, IN2 => XSIG010008, OUTPUT => PAR_BIT_GEN ); XCMP8 : XOR2 port map ( IN1 => XSIG010006, IN2 => XSIG010007, OUTPUT => XSIG010009 ); XCMP7 : XOR2 port map ( IN1 => XSIG010004, IN2 => XSIG010005, OUTPUT => XSIG010007 ); XCMP6 : XOR2 port map ( IN1 => XSIG010002, IN2 => XSIG010003, OUTPUT => XSIG010006 ); XCMP5 : XOR2 port map ( IN1 => PARITY_1_10_Port(9), IN2 => PARITY_1_10_Port(10), OUTPUT => XSIG010008 ); XCMP4 : XOR2 port map ( IN1 => PARITY_1_10_Port(7), IN2 => PARITY_1_10_Port(8), OUTPUT => XSIG010005 ); XCMP3 : XOR2 port map ( IN1 => PARITY_1_10_Port(5), IN2 => PARITY_1_10_Port(6), OUTPUT => XSIG010004 ); XCMP2 : XOR2 port map ( IN1 => PARITY_1_10_Port(3), IN2 => PARITY_1_10_Port(4), OUTPUT => XSIG010003 ); XCMP1 : XOR2 port map ( IN1 => PARITY_1_10_Port(1), IN2 => PARITY_1_10_Port(2), OUTPUT => XSIG010002 ); end architecture arch_PARITY_GEN; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\frame_gen.vhd -- This model generates a 12-bit data frame synchronization code library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE; use IEEE.electrical_systems.all; entity frame_gen is port ( oe : in std_logic := '0'; sync_out : out std_logic_vector (11 downto 0) := "ZZZZZZZZZZZZ"); end entity frame_gen; architecture simple of frame_gen is begin enbl: PROCESS begin wait on OE; if OE = '1' then sync_out <= "010101010101"; -- Sync code else sync_out <= "ZZZZZZZZZZZZ"; end if; end process; end architecture simple; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\shift_reg.vhd -- Parallel input/serial output shift register -- With 4 trailing zeros library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library IEEE; use IEEE.electrical_systems.all; entity shift_reg is generic ( td : time := 0 ns); port ( bus_in : in std_logic_vector ; -- Input bus clk : in std_logic ; -- Shift clock oe : in std_logic ; -- Output enable ser_out : out std_logic := '0'; -- Output port load : in std_logic ; -- Parallel input load clr : in std_logic -- Clear register ); end entity shift_reg; architecture behavioral of shift_reg is begin control_proc : process VARIABLE bit_val : std_logic_vector(11 downto 0); -- Default 12-bit input begin IF (clr = '1' OR clr = 'H') then bit_val := "000000000000"; -- Set all input bits to zero ELSE wait until load'event AND (load = '1' OR load = 'H'); FOR i IN bus_in'high DOWNTO bus_in'low LOOP bit_val(i) := bus_in(i) ; -- Transfer input data to variable END LOOP ; END IF; wait until oe'event AND (oe = '1' OR oe = 'H'); -- Shift if output enabled FOR i IN bit_val'high DOWNTO bit_val'low LOOP wait until clk'event AND (clk = '1' OR clk = 'H'); ser_out <= bit_val(i) ; END LOOP ; FOR i IN 1 TO 4 LOOP -- This loop pads the serial output with 4 zeros wait until clk'event AND (clk = '1' OR clk = 'H'); ser_out <= '0'; END LOOP; END process; end architecture behavioral; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\genhdl\airplane_hcl\tdm_encoder.vhd -- genhdl\airplane_hcl/tdm_encoder.vhd -- Generated by SystemVision netlister 1.0 build 2003.325.1 -- File created Sat Nov 22 14:06:20 2003 library edulib; library ieee; library mgc_ams; use ieee.electrical_systems.all; use ieee.fluidic_systems.all; use ieee.mechanical_systems.all; use ieee.radiant_systems.all; use ieee.std_logic_1164.all; use ieee.thermal_systems.all; use mgc_ams.conversion.all; use work.all; entity TDM_ENCODER is port( signal A2D_DATA : IN STD_LOGIC_VECTOR(1 to 10); signal CLK : IN STD_LOGIC; signal FRM_GEN : IN STD_LOGIC; signal P2S_CLR : IN STD_LOGIC; signal P2S_LOAD : IN STD_LOGIC; signal P2S_OE : IN STD_LOGIC; signal PARITY_OE : IN STD_LOGIC; signal TDM_OUT : OUT STD_LOGIC ); end entity TDM_ENCODER; architecture arch_TDM_ENCODER of TDM_ENCODER is signal SYNC_PAR: STD_LOGIC_VECTOR(0 to 11); component SHIFT_REG generic( TD : TIME:=0NS ); port( signal BUS_IN : IN STD_LOGIC_VECTOR(0 to 11); signal CLK : IN STD_LOGIC; signal OE : IN STD_LOGIC; signal SER_OUT : OUT STD_LOGIC; signal LOAD : IN STD_LOGIC; signal CLR : IN STD_LOGIC ); end component SHIFT_REG; component FRAME_GEN port( signal OE : IN STD_LOGIC; signal SYNC_OUT : OUT STD_LOGIC_VECTOR(11 downto 0) ); end component FRAME_GEN; component PARITY_GEN port( signal OE : IN STD_LOGIC; signal PARITY_1_10_Port : IN STD_LOGIC_VECTOR(1 to 10); signal PARITY_OUT_0_11_Port : OUT STD_LOGIC_VECTOR(0 to 11) ); end component PARITY_GEN; for PAR_GEN1: PARITY_GEN use entity WORK.PARITY_GEN(ARCH_PARITY_GEN); for SYNC_GEN1: FRAME_GEN use entity WORK.FRAME_GEN; for P2S1: SHIFT_REG use entity WORK.SHIFT_REG; begin PAR_GEN1 : PARITY_GEN port map ( OE => PARITY_OE, PARITY_1_10_Port(1) => A2D_DATA(1), PARITY_1_10_Port(2) => A2D_DATA(2), PARITY_1_10_Port(3) => A2D_DATA(3), PARITY_1_10_Port(4) => A2D_DATA(4), PARITY_1_10_Port(5) => A2D_DATA(5), PARITY_1_10_Port(6) => A2D_DATA(6), PARITY_1_10_Port(7) => A2D_DATA(7), PARITY_1_10_Port(8) => A2D_DATA(8), PARITY_1_10_Port(9) => A2D_DATA(9), PARITY_1_10_Port(10) => A2D_DATA(10), PARITY_OUT_0_11_Port(0) => SYNC_PAR(0), PARITY_OUT_0_11_Port(1) => SYNC_PAR(1), PARITY_OUT_0_11_Port(2) => SYNC_PAR(2), PARITY_OUT_0_11_Port(3) => SYNC_PAR(3), PARITY_OUT_0_11_Port(4) => SYNC_PAR(4), PARITY_OUT_0_11_Port(5) => SYNC_PAR(5), PARITY_OUT_0_11_Port(6) => SYNC_PAR(6), PARITY_OUT_0_11_Port(7) => SYNC_PAR(7), PARITY_OUT_0_11_Port(8) => SYNC_PAR(8), PARITY_OUT_0_11_Port(9) => SYNC_PAR(9), PARITY_OUT_0_11_Port(10) => SYNC_PAR(10), PARITY_OUT_0_11_Port(11) => SYNC_PAR(11) ); SYNC_GEN1 : FRAME_GEN port map ( OE => FRM_GEN, SYNC_OUT(11) => SYNC_PAR(0), SYNC_OUT(10) => SYNC_PAR(1), SYNC_OUT(9) => SYNC_PAR(2), SYNC_OUT(8) => SYNC_PAR(3), SYNC_OUT(7) => SYNC_PAR(4), SYNC_OUT(6) => SYNC_PAR(5), SYNC_OUT(5) => SYNC_PAR(6), SYNC_OUT(4) => SYNC_PAR(7), SYNC_OUT(3) => SYNC_PAR(8), SYNC_OUT(2) => SYNC_PAR(9), SYNC_OUT(1) => SYNC_PAR(10), SYNC_OUT(0) => SYNC_PAR(11) ); P2S1 : SHIFT_REG port map ( BUS_IN(0) => SYNC_PAR(0), BUS_IN(1) => SYNC_PAR(1), BUS_IN(2) => SYNC_PAR(2), BUS_IN(3) => SYNC_PAR(3), BUS_IN(4) => SYNC_PAR(4), BUS_IN(5) => SYNC_PAR(5), BUS_IN(6) => SYNC_PAR(6), BUS_IN(7) => SYNC_PAR(7), BUS_IN(8) => SYNC_PAR(8), BUS_IN(9) => SYNC_PAR(9), BUS_IN(10) => SYNC_PAR(10), BUS_IN(11) => SYNC_PAR(11), CLK => CLK, OE => P2S_OE, SER_OUT => TDM_OUT, LOAD => P2S_LOAD, CLR => P2S_CLR ); end architecture arch_TDM_ENCODER; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\a2d_nbit.vhd -- Copyright Mentor Graphics Corporation 2001 -- Confidential Information Provided Under License Agreement for Internal Use Only -- Analog to Digital Converter (Successive Aproximation Register) model with sar architecture (a2d_nbit.vhd) --DESCRIPTION: -- --This is a VHDL-AMS model of a simple analog to digital converter. The model --describes the general behavior of A/D converters for system level design and --verification. --The format of the digital output is binary coding. -- --N.B, dout(n-1) is the MSB while dout(0) is the LSB. -- -- Use IEEE natures and packages library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.electrical_systems.all; entity a2d_nbit is generic ( Vmax: REAL := 4.8 ; -- ADC's maximum range Nbits: INTEGER := 10 ; -- number bits in ADC's output delay: TIME := 10 us -- ADC's conversion time ); port ( signal start: in std_logic ; -- Start signal signal clk: in std_logic ; -- Strobe clock signal oe: in std_logic ; -- Output enable terminal ain: ELECTRICAL ; -- ADC's analog input terminal signal eoc: out std_logic := '0' ; -- End Of Conversion pin signal dout: out std_logic_vector(0 to (Nbits-1))); -- ADC's digital output signal end entity a2d_nbit; architecture sar of a2d_nbit is type states is (input, convert, output) ; -- Three states of A2D Conversion constant bit_range : INTEGER := Nbits-1 ; -- Bit range for dtmp and dout quantity Vin across Iin through ain to electrical_ref; -- ADC's input branch begin sa_adc: process variable thresh: REAL := Vmax ; -- Threshold to test input voltage against variable Vtmp: REAL := Vin ; -- Snapshot of input voltage when conversion starts variable dtmp: std_logic_vector(0 to (Nbits-1)); -- Temp. output data variable status: states := input ; -- Begin with "input" CASE variable bit_cnt: integer := Nbits -1 ; begin CASE status is when input => -- Read input voltages when start goes high wait on start until start = '1' or start = 'H' ; thresh := Vmax ; Vtmp := Vin ; eoc <= '0' ; status := convert ; -- Go to convert state when convert => -- Begin successive approximation conversion thresh := thresh / 2.0 ; -- Get value of MSB wait on clk until clk = '1' OR clk = 'H'; if Vtmp > thresh then dtmp(bit_cnt) := '1' ; Vtmp := Vtmp - thresh ; else dtmp(bit_cnt) := '0' ; end if ; if bit_cnt < 1 then status := output ; -- Go to output state end if; bit_cnt := bit_cnt - 1 ; when output => -- Wait for output enable, then put data on output pins eoc <= '1' after delay ; wait on oe until oe = '1' OR oe = 'H' ; dout <= dtmp ; wait on oe until oe = '0' OR oe = 'L' ; -- Hi Z when OE is low dout <= (others => 'Z') ; bit_cnt := bit_range ; status := input ; -- Set up for next conversion END CASE ; end process sa_adc ; Iin == 0.0 ; -- Ideal input draws no current end architecture sar ; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\genhdl\airplane_hcl\digitize_encode.vhd -- genhdl\airplane_hcl/digitize_encode.vhd -- Generated by SystemVision netlister 1.0 build 2003.325.1 -- File created Sat Nov 22 14:06:20 2003 library edulib; library ieee; library mgc_ams; use ieee.electrical_systems.all; use ieee.fluidic_systems.all; use ieee.mechanical_systems.all; use ieee.radiant_systems.all; use ieee.std_logic_1164.all; use ieee.thermal_systems.all; use mgc_ams.conversion.all; use work.all; entity DIGITIZE_ENCODE is port( terminal CH1_IN : ELECTRICAL; terminal CH2_IN : ELECTRICAL; signal TDM_OUT : OUT STD_LOGIC ); end entity DIGITIZE_ENCODE; architecture arch_DIGITIZE_ENCODE of DIGITIZE_ENCODE is signal SW_CTL: STD_LOGIC; signal A2D_OE: STD_LOGIC; signal CH_BUS: STD_LOGIC_VECTOR(1 to 10); terminal SW_OUT: ELECTRICAL; signal PAR_OE: STD_LOGIC; signal P2S_OE: STD_LOGIC; signal CLK_50: STD_LOGIC; signal A2D_EOC: STD_LOGIC; signal P2S_LOAD: STD_LOGIC; signal A2D_START: STD_LOGIC; signal CLK_100K: STD_LOGIC; signal P2S_CLR: STD_LOGIC; signal FRM_GEN_CTL: STD_LOGIC; signal CLK_6K: STD_LOGIC; component TDM_ENCODER port( signal A2D_DATA : IN STD_LOGIC_VECTOR(1 to 10); signal CLK : IN STD_LOGIC; signal FRM_GEN : IN STD_LOGIC; signal P2S_CLR : IN STD_LOGIC; signal P2S_LOAD : IN STD_LOGIC; signal P2S_OE : IN STD_LOGIC; signal PARITY_OE : IN STD_LOGIC; signal TDM_OUT : OUT STD_LOGIC ); end component TDM_ENCODER; component SM_CNT port( signal A2D_EOC : IN STD_LOGIC; signal A2D_OE : OUT STD_LOGIC; signal A2D_START : OUT STD_LOGIC; signal CH_SEL : OUT STD_LOGIC; signal CLK_100K : IN STD_LOGIC; signal CLK_50 : IN STD_LOGIC; signal CLK_6K : IN STD_LOGIC; signal FRM_GEN : OUT STD_LOGIC; signal P2S_CLR : OUT STD_LOGIC; signal P2S_LOAD : OUT STD_LOGIC; signal P2S_OE : OUT STD_LOGIC; signal PARITY_OE : OUT STD_LOGIC ); end component SM_CNT; component RC_CLK port( signal CLK_100K : OUT STD_LOGIC; signal CLK_50 : OUT STD_LOGIC; signal CLK_6K : OUT STD_LOGIC ); end component RC_CLK; component SWITCH_DIG_2IN generic( R_CLOSED : RESISTANCE:=0.001; R_OPEN : RESISTANCE:=1.0E6; TRANS_TIME : REAL:=0.00001 ); port( signal SW_STATE : IN STD_LOGIC; terminal P_IN1 : ELECTRICAL; terminal P_IN2 : ELECTRICAL; terminal P_OUT : ELECTRICAL ); end component SWITCH_DIG_2IN; component A2D_NBIT port( terminal AIN : ELECTRICAL; signal CLK : IN STD_LOGIC; signal DOUT : OUT STD_LOGIC_VECTOR(0 to 9); signal EOC : OUT STD_LOGIC; signal OE : IN STD_LOGIC; signal START : IN STD_LOGIC ); end component A2D_NBIT; for SWITCH1: SWITCH_DIG_2IN use entity WORK.SWITCH_DIG_2IN; for RC_CLK3: RC_CLK use entity WORK.RC_CLK(ARCH_RC_CLK); for XMTR_STATE_MACHINE: SM_CNT use entity WORK.SM_CNT(ARCH_SM_CNT); for TDM_ENCODER1: TDM_ENCODER use entity WORK.TDM_ENCODER(ARCH_TDM_ENCODER); for A2D_NBIT1: A2D_NBIT use entity WORK.A2D_NBIT; begin SWITCH1 : SWITCH_DIG_2IN port map ( SW_STATE => SW_CTL, P_IN1 => CH1_IN, P_IN2 => CH2_IN, P_OUT => SW_OUT ); RC_CLK3 : RC_CLK port map ( CLK_100K => CLK_100K, CLK_50 => CLK_50, CLK_6K => CLK_6K ); XMTR_STATE_MACHINE : SM_CNT port map ( A2D_EOC => A2D_EOC, A2D_OE => A2D_OE, A2D_START => A2D_START, CH_SEL => SW_CTL, CLK_100K => CLK_100K, CLK_50 => CLK_50, CLK_6K => CLK_6K, FRM_GEN => FRM_GEN_CTL, P2S_CLR => P2S_CLR, P2S_LOAD => P2S_LOAD, P2S_OE => P2S_OE, PARITY_OE => PAR_OE ); TDM_ENCODER1 : TDM_ENCODER port map ( A2D_DATA(1) => CH_BUS(1), A2D_DATA(2) => CH_BUS(2), A2D_DATA(3) => CH_BUS(3), A2D_DATA(4) => CH_BUS(4), A2D_DATA(5) => CH_BUS(5), A2D_DATA(6) => CH_BUS(6), A2D_DATA(7) => CH_BUS(7), A2D_DATA(8) => CH_BUS(8), A2D_DATA(9) => CH_BUS(9), A2D_DATA(10) => CH_BUS(10), CLK => CLK_6K, FRM_GEN => FRM_GEN_CTL, P2S_CLR => P2S_CLR, P2S_LOAD => P2S_LOAD, P2S_OE => P2S_OE, PARITY_OE => PAR_OE, TDM_OUT => TDM_OUT ); A2D_NBIT1 : A2D_NBIT port map ( AIN => SW_OUT, CLK => CLK_100K, DOUT(0) => CH_BUS(1), DOUT(1) => CH_BUS(2), DOUT(2) => CH_BUS(3), DOUT(3) => CH_BUS(4), DOUT(4) => CH_BUS(5), DOUT(5) => CH_BUS(6), DOUT(6) => CH_BUS(7), DOUT(7) => CH_BUS(8), DOUT(8) => CH_BUS(9), DOUT(9) => CH_BUS(10), EOC => A2D_EOC, OE => A2D_OE, START => A2D_START ); end architecture arch_DIGITIZE_ENCODE; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\genhdl\airplane_hcl\airplane_hcl.vhd -- genhdl\airplane_hcl/airplane_hcl.vhd -- Generated by SystemVision netlister 1.0 build 2003.325.1 -- File created Sat Nov 22 14:06:20 2003 library edulib; library ieee; library mgc_ams; use ieee.electrical_systems.all; use ieee.fluidic_systems.all; use ieee.mechanical_systems.all; use ieee.radiant_systems.all; use ieee.std_logic_1164.all; use ieee.thermal_systems.all; use mgc_ams.conversion.all; use work.all; entity AIRPLANE_HCL is end entity AIRPLANE_HCL; architecture arch_AIRPLANE_HCL of AIRPLANE_HCL is terminal PLANE_DIR: ELECTRICAL; signal BITSTREAM2: STD_LOGIC; terminal \$1N25\: ROTATIONAL; terminal RUDDER_FB: ELECTRICAL; terminal SERVO_FLTR_IN: ELECTRICAL; terminal ROT2V_OUT: ELECTRICAL; terminal CH2_PW_OUT: ELECTRICAL; terminal CH2_IN: ELECTRICAL; terminal PROP_IN: ELECTRICAL; terminal CH1_IN: ELECTRICAL; terminal RUDDER_HRN_IN: TRANSLATIONAL; terminal MTR_IN: ELECTRICAL; terminal RUDDER_OUT: ROTATIONAL; terminal GEAR_IN: ROTATIONAL_VELOCITY; terminal GEAR_HRN_OUT: TRANSLATIONAL; terminal CH1_PW_OUT: ELECTRICAL; terminal SERVO_IN: ELECTRICAL; signal BITSTREAM1: STD_LOGIC; component HORN_R2T generic( R : REAL:=1.0 ); port( terminal THETA : ROTATIONAL; terminal POS : TRANSLATIONAL ); end component HORN_R2T; component HORN_T2R generic( R : REAL:=1.0 ); port( terminal POS : TRANSLATIONAL; terminal THETA : ROTATIONAL ); end component HORN_T2R; component TRAN_LINKAGE port( terminal P1 : TRANSLATIONAL; terminal P2 : TRANSLATIONAL ); end component TRAN_LINKAGE; component RF_XMTR_RCVR generic( TD : TIME:=0NS ); port( signal TDM_IN : IN STD_LOGIC; signal TDM_OUT : OUT STD_LOGIC ); end component RF_XMTR_RCVR; component GEAR_RV_R generic( RATIO : REAL:=1.0 ); port( terminal ROTV1 : ROTATIONAL_VELOCITY; terminal ROT2 : ROTATIONAL ); end component GEAR_RV_R; component ROT2V generic( K : REAL:=1.0 ); port( terminal INPUT : ROTATIONAL; terminal OUTPUT : ELECTRICAL ); end component ROT2V; component LPF_2_E generic( F1 : REAL:=10.0; F2 : REAL:=100.0; K : REAL:=1.0 ); port( terminal INPUT : ELECTRICAL; terminal OUTPUT : ELECTRICAL ); end component LPF_2_E; component STOP_R generic( ANG_MAX : ANGLE; ANG_MIN : ANGLE:=0.0; DAMP_STOP : REAL:=1.0E-9; K_STOP : REAL ); port( terminal ANG1 : ROTATIONAL; terminal ANG2 : ROTATIONAL ); end component STOP_R; component RUDDER_SERVO port( terminal POS_FB : ELECTRICAL; terminal SERVO_IN : ELECTRICAL; terminal SERVO_OUT : ELECTRICAL ); end component RUDDER_SERVO; component PW2ANA port( terminal ANA_OUT : ELECTRICAL; terminal PW_IN : ELECTRICAL ); end component PW2ANA; component STICK generic( AC_MAG : REAL:=1.0; AC_PHASE : REAL:=0.0; AMPLITUDE : REAL; DF : REAL:=0.0; FREQ : REAL; OFFSET : REAL:=0.0; PHASE : REAL:=0.0 ); port( terminal V_OUT : ELECTRICAL ); end component STICK; component HCL port( terminal OUTPUT : ELECTRICAL; terminal PLANE_POS : ELECTRICAL ); end component HCL; component DCMOTOR_RV generic( D : REAL; J : MOMENT_INERTIA; KT : REAL; L : INDUCTANCE; R_WIND : RESISTANCE ); port( terminal P1 : ELECTRICAL; terminal P2 : ELECTRICAL; terminal SHAFT_ROTV : ROTATIONAL_VELOCITY ); end component DCMOTOR_RV; component DIGITIZE_ENCODE port( terminal CH1_IN : ELECTRICAL; terminal CH2_IN : ELECTRICAL; signal TDM_OUT : OUT STD_LOGIC ); end component DIGITIZE_ENCODE; component DECODE_PW port( signal BIT_STREAM_IN : IN STD_LOGIC; terminal CH1_PW : ELECTRICAL; terminal CH2_PW : ELECTRICAL ); end component DECODE_PW; component PLANE_POS_SRC port( terminal PLANE_POS : ELECTRICAL; terminal RUDDER_FB : ELECTRICAL ); end component PLANE_POS_SRC; component RUDDER generic( K : REAL:=1.0; THETA_0 : REAL:=0.0 ); port( terminal ROT : ROTATIONAL ); end component RUDDER; for RUDDER_SERVO2: RUDDER_SERVO use entity WORK.RUDDER_SERVO(ARCH_RUDDER_SERVO); for RF_TX_RX: RF_XMTR_RCVR use entity WORK.RF_XMTR_RCVR; for THROTTLE: STICK use entity WORK.STICK; for RUDDER1: RUDDER use entity WORK.RUDDER; for LINKAGE1: TRAN_LINKAGE use entity WORK.TRAN_LINKAGE; for STOP1: STOP_R use entity EDULIB.STOP_R; for MOTOR1: DCMOTOR_RV use entity EDULIB.DCMOTOR_RV; for RUDDER_HORN: HORN_T2R use entity WORK.HORN_T2R; for GEAR_HORN: HORN_R2T use entity WORK.HORN_R2T; for POTENTIOMETER1: ROT2V use entity WORK.ROT2V; for HCL1: HCL use entity WORK.HCL(ARCH_HCL); for GEAR1: GEAR_RV_R use entity WORK.GEAR_RV_R; for PLANE1: PLANE_POS_SRC use entity WORK.PLANE_POS_SRC(ARCH_PLANE_POS_SRC); for ROT2V_RUDDER: ROT2V use entity WORK.ROT2V; for DECODE_PW1: DECODE_PW use entity WORK.DECODE_PW(ARCH_DECODE_PW); for PW2ANA_RUDDER: PW2ANA use entity WORK.PW2ANA(ARCH_PW2ANA); for PW2ANA_THROTTLE: PW2ANA use entity WORK.PW2ANA(ARCH_PW2ANA); for LPF2: LPF_2_E use entity WORK.LPF_2_E; for DIGITIZE_ENCODE1: DIGITIZE_ENCODE use entity WORK.DIGITIZE_ENCODE(ARCH_DIGITIZE_ENCODE); begin RUDDER_SERVO2 : RUDDER_SERVO port map ( POS_FB => ROT2V_OUT, SERVO_IN => SERVO_IN, SERVO_OUT => MTR_IN ); RF_TX_RX : RF_XMTR_RCVR port map ( TDM_IN => BITSTREAM1, TDM_OUT => BITSTREAM2 ); THROTTLE : STICK generic map ( AMPLITUDE => 2.397, FREQ => 1.0, OFFSET => 2.397, PHASE => 0.0 ) port map ( V_OUT => CH1_IN ); RUDDER1 : RUDDER generic map ( K => 0.2 ) port map ( ROT => RUDDER_OUT ); LINKAGE1 : TRAN_LINKAGE port map ( P1 => GEAR_HRN_OUT, P2 => RUDDER_HRN_IN ); STOP1 : STOP_R generic map ( ANG_MAX => 1.05, ANG_MIN => -1.05, DAMP_STOP => 1.0E2, K_STOP => 1.0E6 ) port map ( ANG1 => \$1N25\, ANG2 => ROTATIONAL_REF ); MOTOR1 : DCMOTOR_RV generic map ( D => 5.63E-6, J => 168.0E-9, KT => 3.43E-3, L => 2.03E-3, R_WIND => 2.2 ) port map ( P1 => MTR_IN, P2 => ELECTRICAL_REF, SHAFT_ROTV => GEAR_IN ); RUDDER_HORN : HORN_T2R port map ( POS => RUDDER_HRN_IN, THETA => RUDDER_OUT ); GEAR_HORN : HORN_R2T port map ( THETA => \$1N25\, POS => GEAR_HRN_OUT ); POTENTIOMETER1 : ROT2V generic map ( K => 1.0 ) port map ( INPUT => \$1N25\, OUTPUT => ROT2V_OUT ); HCL1 : HCL port map ( OUTPUT => CH2_IN, PLANE_POS => PLANE_DIR ); GEAR1 : GEAR_RV_R generic map ( RATIO => 0.01 ) port map ( ROTV1 => GEAR_IN, ROT2 => \$1N25\ ); PLANE1 : PLANE_POS_SRC port map ( PLANE_POS => PLANE_DIR, RUDDER_FB => RUDDER_FB ); ROT2V_RUDDER : ROT2V generic map ( K => 4.57 ) port map ( INPUT => RUDDER_OUT, OUTPUT => RUDDER_FB ); DECODE_PW1 : DECODE_PW port map ( BIT_STREAM_IN => BITSTREAM2, CH1_PW => CH1_PW_OUT, CH2_PW => CH2_PW_OUT ); PW2ANA_RUDDER : PW2ANA port map ( ANA_OUT => SERVO_FLTR_IN, PW_IN => CH2_PW_OUT ); PW2ANA_THROTTLE : PW2ANA port map ( ANA_OUT => PROP_IN, PW_IN => CH1_PW_OUT ); LPF2 : LPF_2_E generic map ( F1 => 10.0, F2 => 10.0 ) port map ( INPUT => SERVO_FLTR_IN, OUTPUT => SERVO_IN ); DIGITIZE_ENCODE1 : DIGITIZE_ENCODE port map ( CH1_IN => CH1_IN, CH2_IN => CH2_IN, TDM_OUT => BITSTREAM1 ); end architecture arch_AIRPLANE_HCL; --