-- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\Electrical/v_sine.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : v_sine.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2003-05-13 ------------------------------------------------------------------------------- -- Description: Electrical sinusoidal voltage source -- Includes frequency domain settings ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created -- 2001/07/03 1.1 Mentor Graphics Changed generics from real to -- voltage. ------------------------------------------------------------------------------- library IEEE; use IEEE.MATH_REAL.all; -- Use IEEE natures and packages use IEEE.ELECTRICAL_SYSTEMS.all; entity v_sine is generic ( freq : real; -- frequency [Hertz] amplitude : voltage; -- amplitude [Volts] phase : real := 0.0; -- initial phase [Degrees] offset : voltage := 0.0; -- DC value [Volts] df : real := 0.0; -- damping factor [1/second] ac_mag : voltage := 1.0; -- AC magnitude [Volts] ac_phase : real := 0.0); -- AC phase [Degrees] port ( terminal pos, neg : electrical); end entity v_sine; ------------------------------------------------------------------------------- -- Ideal Architecture ------------------------------------------------------------------------------- architecture ideal of v_sine is -- Declare Branch Quantities quantity v across i through pos to neg; -- Declare Quantity for Phase in radians (calculated below) quantity phase_rad : real; -- Declare Quantity in frequency domain for AC analysis quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0; begin -- Convert phase to radians phase_rad == math_2_pi *(freq * NOW + phase / 360.0); if domain = quiescent_domain or domain = time_domain use v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df); else v == ac_spec; -- used for Frequency (AC) analysis end use; end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\diode_pwl.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : diode_pwl.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2001/06/16 ------------------------------------------------------------------------------- -- Description: Diode model with ideal architecture -- Currently no Generics due to bug in DV ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- library IEEE; use IEEE.math_real.all; -- Use proposed IEEE natures and packages library IEEE; use IEEE.electrical_systems.all; -- energy_systems package needed for Boltzmann constant (K = Joules/Kelvin) use IEEE.FUNDAMENTAL_CONSTANTS.all; use IEEE.MATERIAL_CONSTANTS.all; use IEEE.energy_systems.all; ENTITY diode_pwl IS GENERIC ( ron : real; -- equivalent series resistance roff : real); -- leakage resistance PORT ( TERMINAL p, -- positive pin m : electrical); -- minus pin END ENTITY diode_pwl; ARCHITECTURE simple OF diode_pwl IS QUANTITY v across i through p TO m; BEGIN -- simple ARCHITECTURE if v'Above(0.0) use i == v/ron; elsif not v'Above(0.0) use i == v/roff; else i == 0.0; end use; break on v'Above(0.0); END ARCHITECTURE simple; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\prop_pwl.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : prop_pwl.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2001/06/16 ------------------------------------------------------------------------------- -- Description: Propeller Load (Rotational_V domain) ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- library ieee; use ieee.math_real.all; package pwl_functions is function pwl_dim1_extrap (x : in real; xdata, ydata : in real_vector ) return real; function interpolate (x,y2,y1,x2,x1 : in real) return real; function extrapolate (x,y2,y1,x2,x1 : in real) return real; end package pwl_functions; package body pwl_functions is function interpolate (x,y2,y1,x2,x1 : in real) return real is variable m, yvalue : real; begin assert (x1 /= x2) report "interpolate: x1 cannot be equal to x2" severity error; assert (x >= x1) and (x <= x2) report "interpolate: x must be between x1 and x2, inclusively " severity error; m := (y2 - y1)/(x2 - x1); yvalue := y1 + m*(x - x1); return yvalue; end function interpolate; function extrapolate (x,y2,y1,x2,x1 : in real) return real is variable m, yvalue : real; begin assert (x1 /= x2) report "extrapolate: x1 cannot be equal to x2" severity error; assert (x <= x1) or (x >= x2) report "extrapolate: x is within x1, x2 bounds; interpolation will be performed" severity warning; m := (y2 - y1)/(x2 - x1); yvalue := y1 + m*(x - x1); return yvalue; end function extrapolate; -- JMD August 6, 2001. Created a new pwl_dim1_extrap function that returns extrapolated yvalue for "out-of-range" x value. function pwl_dim1_extrap (x : in real; xdata, ydata : in real_vector ) return real is variable xvalue, yvalue, m : real; variable start, fin, mid: integer; begin if x <= xdata(0) then yvalue := extrapolate(x,ydata(1),ydata(0),xdata(1),xdata(0)); return yvalue; end if; if x >= xdata(xdata'right) then yvalue := extrapolate(x,ydata(ydata'right),ydata(ydata'right-1),xdata(xdata'right),xdata(xdata'right-1)); return yvalue; end if; start:=0; fin:=xdata'right; -- I assume that the valid elements are from xdata(0) to xdata(fin), inclusive. -- so fin==n-1 in C terms (where n is the size of the array). while start <=fin loop mid:=(start+fin)/2; if xdata(mid) < x then start:=mid+1; else fin:=mid-1; end if; end loop; if xdata(mid) > x then mid:=mid-1; end if; yvalue := interpolate(x,ydata(mid+1),ydata(mid),xdata(mid+1),xdata(mid)); return yvalue; end function pwl_dim1_extrap; end package body pwl_functions; library IEEE; use IEEE.mechanical_systems.all; library ieee; use ieee.math_real.all; use work.pwl_functions.all; entity prop_pwl is generic ( ydata : real_vector; -- torque data xdata : real_vector -- velocity data ); port (terminal shaft1 : ROTATIONAL_VELOCITY); end entity prop_pwl; architecture ideal of prop_pwl is quantity w across torq through shaft1 to ROTATIONAL_VELOCITY_REF; begin torq == pwl_dim1_extrap(w, xdata, ydata); end architecture ideal; -- -- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\Electrical/v_pulse.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : v_pulse.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2003-05-13 ------------------------------------------------------------------------------- -- Description: Voltage Pulse Source -- Includes Frequency Domain settings ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created -- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type -- time. Uses time2real function. -- Pulsewidth no longer includes -- rise and fall times. -- 2002-06-06 1.2 Mentor Graphics Fixed bug when delay=0 ------------------------------------------------------------------------------- library IEEE; use IEEE.MATH_REAL.all; -- Use IEEE natures and packages use IEEE.electrical_systems.all; entity v_pulse is generic ( initial : voltage := 0.0; -- initial value [Volts] pulse : voltage; -- pulsed value [Volts] ti2p : time := 1ns; -- initial to pulse [Sec] tp2i : time := 1ns; -- pulse to initial [Sec] delay : time := 0ms; -- delay time [Sec] width : time; -- duration of pulse [Sec] period : time; -- period [Sec] ac_mag : voltage := 1.0; -- AC magnitude [Volts] ac_phase : real := 0.0); -- AC phase [Degrees] port ( terminal pos, neg : electrical); end entity v_pulse; ------------------------------------------------------------------------------- -- Ideal Architecture ------------------------------------------------------------------------------- architecture ideal of v_pulse is -- Declare Through and Across Branch Quantities quantity v across i through pos to neg; -- Declare quantity in frequency domain for AC analysis quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0; -- Signal used in CreateEvent process below signal pulse_signal : voltage := initial; -- Function to convert numbers of type TIME to type REAL function time2real(tt : time) return real is begin return time'pos(tt) * 1.0e-15; end time2real; -- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute) constant ri2p : real := time2real(ti2p); constant rp2i : real := time2real(tp2i); begin if domain = quiescent_domain or domain = time_domain use v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions else v == ac_spec; -- used for Frequency (AC) analysis end use; -- purpose: Create events to define pulse shape -- type : combinational -- inputs : -- outputs: pulse_signal CreateEvent : process begin wait until domain = time_domain; -- Run process in Time Domain only wait for delay; loop pulse_signal <= pulse; wait for (width + ti2p); pulse_signal <= initial; wait for (period - width - ti2p); end loop; end process CreateEvent; end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- -- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\MixedSignal/comparator_d.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : comparator_d.vhd -- Author : Mentor Graphics -- Created : 2001/08/03 -- Last update: 2003-05-13 ------------------------------------------------------------------------------- -- Description: Voltage comparator with digital output ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/08/03 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- -- Use IEEE natures and packages library IEEE; use ieee.std_logic_1164.all; use IEEE.ELECTRICAL_SYSTEMS.all; entity comparator_d is port ( terminal in_pos : electrical; terminal in_neg : electrical; signal output : out std_logic := '1' -- Digital output ); end comparator_d; ------------------------------------------------------------------------------- -- Behavioral architecture ------------------------------------------------------------------------------- architecture behavioral of comparator_d is quantity Vin across in_pos; quantity Vref across in_neg; begin -- behavioral -- purpose: Detect threshold crossing and assign event on output -- type : combinational -- inputs : vin'above(thres) -- outputs: pulse_signal process (Vin'above(Vref)) is begin -- PROCESS if Vin'above(Vref) then output <= '1' after 1us; else output <= '0' after 1us; end if; end process; end behavioral; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- -- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\Electrical/resistor.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : resistor.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2002-05-24 ------------------------------------------------------------------------------- -- Description: Electrical Resistor ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- -- Use proposed IEEE natures and packages library IEEE; use IEEE.electrical_systems.all; entity resistor is generic ( res : resistance); -- resistance (no initial value) port ( terminal p1, p2 : electrical); end entity resistor; ------------------------------------------------------------------------------- -- Ideal Architecture (V = I*R) ------------------------------------------------------------------------------- architecture ideal of resistor is quantity v across i through p1 to p2; begin -- Fundamental equation v == i*res; end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- -- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\Electrical/v_constant.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : v_constant.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2003-10-02 ------------------------------------------------------------------------------- -- Description: Constant Voltage Source -- Includes Frequency Domain settings ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- library IEEE; use IEEE.MATH_REAL.all; -- Use IEEE natures and packages use IEEE.electrical_systems.all; entity v_constant is generic ( level : voltage; -- Constant voltage value [Volts] ac_mag : voltage := 0.0; -- AC magnitude [Volts] ac_phase : real := 0.0); -- AC phase [Degrees] port ( terminal pos, neg : electrical); end entity v_constant; ------------------------------------------------------------------------------- -- Ideal Architecture (I = constant) ------------------------------------------------------------------------------- architecture ideal of v_constant is -- Declare Branch Quantities quantity v across i through pos to neg; -- Declare quantity in frequency domain for AC analysis quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0; begin if domain = quiescent_domain or domain = time_domain use v == level; else v == ac_spec; -- used for Frequency (AC) analysis end use; end architecture ideal; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\opamp.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : opamp.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2001/06/16 ------------------------------------------------------------------------------- -- Description: 3-pin OpAmp model with behavioral architecture -- Uses Q'LTF function to define open-loop response ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- library IEEE; use IEEE.math_real.all; -- Use proposed IEEE natures and packages library IEEE; use IEEE.electrical_systems.all; entity opamp is -- Initialize parameters generic (rin : resistance := 1.0e6; -- Input resistance [Ohms] rout : resistance := 100.0; -- Output resistance (Ohms] avol : real := 100.0e3; -- Open loop gain f_0dB : real := 1.0e6 -- Unity Gain Frequency [Hz] ); -- Define ports as electrical terminals port ( terminal in_pos, in_neg, output : electrical); end entity opamp; ------------------------------------------------------------------------------- -- Basic Architecture -- Characteristics modeled: -- 1. Open loop gain -- 2. Frequency characteristics (single pole response) -- 3. Input and output resistance -- Uses Q'Ltf function to create open loop gain and roll off ------------------------------------------------------------------------------- architecture basic of opamp is -- Declare constants constant f_3db : real := f_0db / avol; -- -3dB frequency constant w_3dB : real := math_2_pi*f_3dB; -- -3dB freq in radians -- Numerator and denominator for Q'LTF function constant num : real_vector := (0 => avol); constant den : real_vector := (1.0, 1.0/w_3dB); -- Declare input and output quantities quantity v_in across i_in through in_pos to in_neg; quantity v_out across i_out through output; begin -- ARCHITECTURE basic i_in == v_in / rin; -- input current v_out == v_in'ltf(num, den) + i_out*rout; -- output voltage end architecture basic; ------------------------------------------------------------------------------- -- Copyright (c) 2001 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\genhdl\airplane_prop\pwm_mac.vhd -- genhdl\airplane_prop/pwm_mac.vhd -- Generated by SystemVision netlister 1.0 build 2003.315.1 -- File created Tue Nov 18 14:23:53 2003 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.electrical_systems.all; USE ieee.mechanical_systems.all; USE ieee.fluidic_systems.all; USE ieee.thermal_systems.all; USE ieee.radiant_systems.all; LIBRARY edulib; USE work.all; entity PWM_MAC is port( signal DIG_OUT : OUT STD_LOGIC; terminal INM : ELECTRICAL; terminal INP : ELECTRICAL ); end entity PWM_MAC; architecture arch_PWM_MAC of PWM_MAC is terminal XSIG010002: ELECTRICAL; terminal XSIG010003: ELECTRICAL; terminal PLSE_IN: ELECTRICAL; terminal CMP_IN: ELECTRICAL; component V_PULSE generic( AC_MAG : VOLTAGE:=0.0; AC_PHASE : REAL:=0.0; DELAY : TIME:=0 MS; INITIAL : VOLTAGE:=0.0; PERIOD : TIME; PULSE : VOLTAGE; TI2P : TIME:=1 NS; TP2I : TIME:=1 NS; WIDTH : TIME ); port( terminal POS : ELECTRICAL; terminal NEG : ELECTRICAL ); end component V_PULSE; component V_CONSTANT generic( AC_MAG : VOLTAGE:=0.0; AC_PHASE : REAL:=0.0; LEVEL : VOLTAGE ); port( terminal POS : ELECTRICAL; terminal NEG : ELECTRICAL ); end component V_CONSTANT; component RESISTOR generic( RES : RESISTANCE ); port( terminal P1 : ELECTRICAL; terminal P2 : ELECTRICAL ); end component RESISTOR; component OPAMP generic( AVOL : REAL:=100.0E3; F_0DB : REAL:=1.0E6; RIN : RESISTANCE:=1.0E6; ROUT : RESISTANCE:=100.0 ); port( terminal IN_POS : ELECTRICAL; terminal IN_NEG : ELECTRICAL; terminal OUTPUT : ELECTRICAL ); end component OPAMP; component COMPARATOR_D port( terminal IN_POS : ELECTRICAL; terminal IN_NEG : ELECTRICAL; signal OUTPUT : OUT STD_LOGIC := '1' ); end component COMPARATOR_D; for V9: V_PULSE use entity EDULIB.V_PULSE; for COMP1: COMPARATOR_D use entity EDULIB.COMPARATOR_D; for R3: RESISTOR use entity EDULIB.RESISTOR(IDEAL); for R2: RESISTOR use entity EDULIB.RESISTOR(IDEAL); for V2: V_CONSTANT use entity EDULIB.V_CONSTANT; for R1: RESISTOR use entity EDULIB.RESISTOR(IDEAL); for U1: OPAMP use entity WORK.OPAMP; begin V9 : V_PULSE generic map ( DELAY => 1 US, INITIAL => -4.7, PERIOD => 405 US, PULSE => 4.7, TI2P => 200 US, TP2I => 200 US, WIDTH => 1 US ) port map ( POS => PLSE_IN, NEG => ELECTRICAL_REF ); COMP1 : COMPARATOR_D port map ( IN_POS => XSIG010003, IN_NEG => CMP_IN, OUTPUT => DIG_OUT ); R3 : RESISTOR generic map ( RES => 10.0E3 ) port map ( P1 => INP, P2 => XSIG010002 ); R2 : RESISTOR generic map ( RES => 10.0E3 ) port map ( P1 => PLSE_IN, P2 => XSIG010002 ); V2 : V_CONSTANT generic map ( LEVEL => 0.0 ) port map ( POS => XSIG010003, NEG => ELECTRICAL_REF ); R1 : RESISTOR generic map ( RES => 10.0E3 ) port map ( P1 => XSIG010002, P2 => CMP_IN ); U1 : OPAMP port map ( IN_POS => INM, IN_NEG => XSIG010002, OUTPUT => CMP_IN ); end architecture arch_PWM_MAC; -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\hdl\switch_dig_log.vhd library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.math_real.all; library IEEE; use IEEE.electrical_systems.all; entity switch_dig_log is generic ( trans_time : real := 1.0e-9; r_closed : resistance := 1.0e-3; r_open : resistance := 1.0e6 ); port ( terminal p1 : electrical ; sw_state : in std_logic ; terminal p2 : electrical ); begin end switch_dig_log ; ----------------------------------------------------------------------------------------- architecture linear of switch_dig_log is signal r_sig : resistance := r_open; -- create internal signal for CreateState process quantity v across i through p1 to p2; quantity r : resistance; begin -- purpose: Detect Switch state and assign resistance value to r_sig -- type : combinational -- inputs : sw_state -- outputs: r_sig DetectState: process (sw_state) begin -- process DetectState if (sw_state'event and sw_state = '0') then r_sig <= r_open; elsif (sw_state'event and sw_state = '1') then r_sig <= r_closed; end if; end process DetectState; -- Characteristic equations r == r_sig'ramp(trans_time, trans_time); v == r*i; end architecture linear; ------------------------------------------------------------------------------------------- architecture log of switch_dig_log is constant log10_r_open : real := log10(r_open); constant log10_r_closed : real := log10(r_closed); signal log10_r_sig : resistance := log10_r_open; -- create internal signal for CreateState process quantity v across i through p1 to p2; quantity r : resistance; quantity log10_r : real; begin -- purpose: Detect Switch state and assign resistance value to r_sig -- type : combinational -- inputs : sw_state -- outputs: r_sig DetectState: process (sw_state) begin -- process DetectState if (sw_state'event and sw_state = '0') then log10_r_sig <= log10_r_open; elsif (sw_state'event and sw_state = '1') then log10_r_sig <= log10_r_closed; end if; end process DetectState; -- Characteristic equations log10_r == log10_r_sig'ramp(trans_time, trans_time); r == 10**log10_r; v == r*i; end architecture log; -- -- c:\epd\SystemVision.1\sim\2003.2\systemvision\win32\edulib\v3.0_2.1\MixedTechnology/DCMotor_rv.vhd ------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation -- -- This model is a component of the Mentor Graphics VHDL-AMS educational open -- source model library, and is covered by this license agreement. This model, -- including any updates, modifications, revisions, copies, and documentation -- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR -- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH -- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive -- license to use, reproduce, modify and distribute this model, provided that: -- (a) no fee or other consideration is charged for any distribution except -- compilations distributed in accordance with Section (d) of this license -- agreement; (b) the comment text embedded in this model is included verbatim -- in each copy of this model made or distributed by you, whether or not such -- version is modified; (c) any modified version must include a conspicuous -- notice that this model has been modified and the date of modification; and -- (d) any compilations sold by you that include this model must include a -- conspicuous notice that this model is available from Mentor Graphics in its -- original form at no charge. -- -- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR -- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF -- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL -- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER. ------------------------------------------------------------------------------- -- File : DCMotor_rv.vhd -- Author : Mentor Graphics -- Created : 2001/06/16 -- Last update: 2003-05-23 ------------------------------------------------------------------------------- -- Description: Basic DC Motor with output of type ROTATIONAL_VELOCITY ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/06/16 1.0 Mentor Graphics Created ------------------------------------------------------------------------------- -- Use proposed IEEE natures and packages library IEEE; use IEEE.mechanical_systems.all; use IEEE.electrical_systems.all; entity DCMotor_rv is generic ( r_wind : resistance; -- Motor winding resistance [Ohm] kt : real; -- Torque coefficient [N*m/Amp] l : inductance; -- Winding inductance [Henrys] d : real; -- Damping coefficient [N*m/(rad/sec)] j : moment_inertia); -- Moment of inertia [kg*meter**2] port (terminal p1, p2 : electrical; terminal shaft_rotv : rotational_velocity); end entity DCMotor_rv; ------------------------------------------------------------------------------- -- Basic Architecture -- Motor equations: V = Kt*W + I*Rwind + L*dI/dt -- T = -Kt*I + D*W + J*dW/dt ------------------------------------------------------------------------------- architecture basic of DCMotor_rv is quantity v across i through p1 to p2; quantity w across torq through shaft_rotv to rotational_velocity_ref; begin torq == -1.0*kt*i + d*w + j*w'dot; v == kt*w + i*r_wind + l*i'dot; end architecture basic; ------------------------------------------------------------------------------- -- Copyright (c) 2003 Mentor Graphics Corporation ------------------------------------------------------------------------------- -- -- C:\Mentor_Projects\CS5_RC_Airplane_System\genhdl\airplane_prop\airplane_prop.vhd -- genhdl\airplane_prop/airplane_prop.vhd -- Generated by SystemVision netlister 1.0 build 2003.315.1 -- File created Tue Nov 18 14:23:53 2003 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.electrical_systems.all; USE ieee.mechanical_systems.all; USE ieee.fluidic_systems.all; USE ieee.thermal_systems.all; USE ieee.radiant_systems.all; LIBRARY edulib; USE work.all; entity AIRPLANE_PROP is end entity AIRPLANE_PROP; architecture arch_AIRPLANE_PROP of AIRPLANE_PROP is terminal PROP: ROTATIONAL_VELOCITY; terminal PROP_AMP_IN: ELECTRICAL; signal PWM_OUT: STD_LOGIC; terminal PROP_PWR: ELECTRICAL; terminal PROP_MTR_IN: ELECTRICAL; component DIODE_PWL generic( ROFF : REAL; RON : REAL ); port( terminal P : ELECTRICAL; terminal M : ELECTRICAL ); end component DIODE_PWL; component SWITCH_DIG_LOG generic( R_CLOSED : RESISTANCE:=1.0E-3; R_OPEN : RESISTANCE:=1.0E6; TRANS_TIME : REAL:=1.0E-9 ); port( terminal P1 : ELECTRICAL; signal SW_STATE : IN STD_LOGIC; terminal P2 : ELECTRICAL ); end component SWITCH_DIG_LOG; component V_SINE generic( AC_MAG : VOLTAGE:=0.0; AC_PHASE : REAL:=0.0; AMPLITUDE : VOLTAGE; DF : REAL:=0.0; FREQ : REAL; OFFSET : VOLTAGE:=0.0; PHASE : REAL:=0.0 ); port( terminal POS : ELECTRICAL; terminal NEG : ELECTRICAL ); end component V_SINE; component PROP_PWL generic( XDATA : REAL_VECTOR; YDATA : REAL_VECTOR ); port( terminal SHAFT1 : ROTATIONAL_VELOCITY ); end component PROP_PWL; component V_CONSTANT generic( AC_MAG : VOLTAGE:=0.0; AC_PHASE : REAL:=0.0; LEVEL : VOLTAGE ); port( terminal POS : ELECTRICAL; terminal NEG : ELECTRICAL ); end component V_CONSTANT; component DCMOTOR_RV generic( D : REAL; J : MOMENT_INERTIA; KT : REAL; L : INDUCTANCE; R_WIND : RESISTANCE ); port( terminal P1 : ELECTRICAL; terminal P2 : ELECTRICAL; terminal SHAFT_ROTV : ROTATIONAL_VELOCITY ); end component DCMOTOR_RV; component PWM_MAC port( signal DIG_OUT : OUT STD_LOGIC; terminal INM : ELECTRICAL; terminal INP : ELECTRICAL ); end component PWM_MAC; for V8: V_SINE use entity EDULIB.V_SINE; for D4: DIODE_PWL use entity WORK.DIODE_PWL; for PROP1: PROP_PWL use entity WORK.PROP_PWL; for PWM1: PWM_MAC use entity WORK.PWM_MAC(ARCH_PWM_MAC); for SW2: SWITCH_DIG_LOG use entity WORK.SWITCH_DIG_LOG(LINEAR); for V4: V_CONSTANT use entity EDULIB.V_CONSTANT; for MOTOR2: DCMOTOR_RV use entity EDULIB.DCMOTOR_RV; begin V8 : V_SINE generic map ( AMPLITUDE => 2.3, FREQ => 1.0, OFFSET => 2.3, PHASE => 0.0 ) port map ( POS => PROP_AMP_IN, NEG => ELECTRICAL_REF ); D4 : DIODE_PWL generic map ( ROFF => 100.0E3, RON => 0.001 ) port map ( P => ELECTRICAL_REF, M => PROP_MTR_IN ); PROP1 : PROP_PWL generic map ( XDATA => (471.2, 523.6, 576.0, 628.3, 680.7, 733.0, 785.4, 837.7, 890.0, 942.5, 994.8), YDATA => (0.233, 0.2865, 0.347, 0.4138, 0.485, 0.563, 0.645, 0.735, 0.830, 0.93, 1.08) ) port map ( SHAFT1 => PROP ); PWM1 : PWM_MAC port map ( DIG_OUT => PWM_OUT, INM => ELECTRICAL_REF, INP => PROP_AMP_IN ); SW2 : SWITCH_DIG_LOG generic map ( R_CLOSED => 1.0E-6, TRANS_TIME => 1.0E-4 ) port map ( P1 => PROP_PWR, SW_STATE => PWM_OUT, P2 => PROP_MTR_IN ); V4 : V_CONSTANT generic map ( LEVEL => 42.0 ) port map ( POS => PROP_PWR, NEG => ELECTRICAL_REF ); MOTOR2 : DCMOTOR_RV generic map ( D => 5.63E-12, J => 315.0E-6, KT => 30.1E-3, L => 40.0E-6, R_WIND => 0.16 ) port map ( P1 => PROP_MTR_IN, P2 => ELECTRICAL_REF, SHAFT_ROTV => PROP ); end architecture arch_AIRPLANE_PROP; --