SUAVE

SAVANT and University of Adelaide VHDL Extensions

Background

VHDL is an IEEE-standard hardware description language used in the design of digital electronic systems. Designers use the
language to develop models of systems, to verify their correctness using simulation, and to refine them using synthesis.

As integrated circuit complexity extends into the millions of gates, designers must increasingly rely on use of hardware
description languages for high-level design early in the design flow. High-level design involves description of the system at a
high-level of abstraction, ignoring lower-level details of implementation. At the high level, the designer makes decisions about
the algorithms to be used and explores alternative architectures for implementing the algorithms.

VHDL originated in the early 1980s, and provides very good facilities for modelling at the gate and register-transfer levels of
abstraction. Its facilities for high-level modelling, however, are less than satisfactory. The SUAVE project, a collaborative
project between Dr. Peter Ashenden at the University of Adelaide and Dr. Philip Wilsey at the University of Cincinnati, has
extended VHDL to improve its support for high-level modelling. Extensions include object-oriented features for improved data modelling, type generics for improved reuse of model components, and message-passing communication via channels for
improved system-level modelling. These extensions are currently being implemented in experimental tools for design analysis
and simulation. The extensions have also been presented to the IEEE as a candidate for standardisation.

Work is in progress to implement the SAUVE extensions, and a SUAVE analyzer (version 0.9.02) is available. The analyzer is built on top of the SAVANT software and is limited by the license restrictions of that software.

IEEE DASC OOVHDL Working Group

We have presented SUAVE to the IEEE Design Automation Standards Committee (DASC) OOVHDL Working Group as a strawman for OO extensions to VHDL. You can subscribe to the email list by sending email to majordomo@eda.org with the text

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The Working Group has undertaken a review of the SUAVE proposal and the Objective VHDL proposal. It has decided to base standardization work on the Objective VHDL proposal, but will consider including aspects of SUAVE.

SUAVE Tutorial (updated 17 March 1999)

A tutorial presentation is available in the following formats:

The source code examples from the tutorial are also available:

Selected Publications

P. J. Ashenden, P. A. Wilsey and D. E. Martin, SUAVE Language Description, Technical Report 99/04, Dept Computer Science, The University of Adelaide, South Australia (July 1999). [PDF]

P. J. Ashenden and P. A. Wilsey, "Principles for Extensions to VHDL for High-Level Modeling," VLSI Design, Vol. 10, No. 2 (1999), pp. 217-236.

P. J. Ashenden, P. A. Wilsey and D. E. Martin, "SUAVE: Extending VHDL to Improve Modeling Support," IEEE Design and Test of Computers (April-June 1998), pp. 34-44.

P. J. Ashenden and P. A. Wilsey, "Considerations on System-Level Behavioural and Structural Modeling Extensions to VHDL," Proceedings of VHDL International Users Forum Spring-98 Conference, Santa Clara, California (March 1998), pp. 42-50 (winner of Best Paper prize). [PDF]

PDF documents can be viewed with Adobe Acrobat Reader.

Peter Ashenden
peter.ashenden@computer.org