----------------------------------------------------------------
-- Chapter 1 Fundamental Concepts
----------------------------------------------------------------

----------------------------------------------------------------
-- 1.1 Modeling Digital Systems
----------------------------------------------------------------

----------------------------------------------------------------
-- 1.2 Domains and Levels of Modeling
----------------------------------------------------------------

----------------------------------------------------------------
-- 1.2.1 Modeling Example
----------------------------------------------------------------

----------------------------------------------------------------
-- 1.3 Modeling Languages
----------------------------------------------------------------

----------------------------------------------------------------
-- 1.4 VHDL Modeling Concepts
----------------------------------------------------------------

-- Example 1.1

entity reg4 is
  port ( d0, d1, d2, d3, en, clk : in bit;
         q0, q1, q2, q3 : out  bit );
end entity reg4;

----------------------------------------------------------------
-- 1.4.1 Elements of Behavior
----------------------------------------------------------------

-- Example 1.2

architecture behav of reg4 is
begin

  storage : process is
    variable stored_d0, stored_d1, stored_d2, stored_d3 : bit;
  begin
    wait until clk;
    if en then
      stored_d0 := d0;
      stored_d1 := d1;
      stored_d2 := d2;
      stored_d3 := d3;
    end if;
    q0 <= stored_d0 after 5 ns;
    q1 <= stored_d1 after 5 ns;
    q2 <= stored_d2 after 5 ns;
    q3 <= stored_d3 after 5 ns;
  end process storage;

end architecture behav;

----------------------------------------------------------------
-- 1.4.2 Elements of Structure
----------------------------------------------------------------

-- Example 1.3

entity d_ff is
  port ( d, clk : in bit;  q : out bit );
end d_ff;

architecture basic of d_ff is
begin
  
  ff_behavior : process is
  begin
    wait until clk;
    q <= d after 2 ns;
  end process ff_behavior;
  
end architecture basic;

entity and2 is
  port ( a, b : in bit;  y : out bit );
end and2;

architecture basic of and2 is
begin

  and2_behavior : process is
  begin
    y <= a and b after 2 ns;
    wait on a, b;
  end process and2_behavior;

end architecture basic;

architecture struct of reg4 is

  signal int_clk : bit;

begin

  bit0 : entity work.d_ff(basic)
    port map (d0, int_clk, q0);
  bit1 : entity work.d_ff(basic)
    port map (d1, int_clk, q1);
  bit2 : entity work.d_ff(basic)
    port map (d2, int_clk, q2);
  bit3 : entity work.d_ff(basic)
    port map (d3, int_clk, q3);

  gate : entity work.and2(basic)
    port map (en, clk, int_clk);

end architecture struct;

----------------------------------------------------------------
-- 1.4.3 Mixed Structural and Behavioral Models
----------------------------------------------------------------

-- Example 1.4

entity multiplier is
  port ( clk, reset : in bit;
         multiplicand, multiplier : in integer;
         product : out integer );
end entity multiplier;

--------------------------------------------------

architecture mixed of multiplier is

  signal partial_product, full_product : integer;
  signal arith_control, result_en, mult_bit, mult_load : bit;

begin -- mixed

  arith_unit : entity work.shift_adder(behavior)
    port map ( addend => multiplicand, augend => full_product,
               sum => partial_product,
               add_control => arith_control);

  result : entity work.reg(behavior)
    port map ( d => partial_product, q => full_product,
               en => result_en, reset => reset);

  multiplier_sr : entity work.shift_reg(behavior)
    port map ( d => multiplier, q => mult_bit,
               load => mult_load, clk => clk);

  product <= full_product;

  control_section : process is
    -- variable declarations for control_section
    -- ...
  begin -- control section
    -- sequential statements to assign values to control signals
    -- ...
    wait on clk, reset;
  end process control_section;

end architecture mixed;

----------------------------------------------------------------
-- 1.4.4 Test Benches
----------------------------------------------------------------

-- Example 1.5

entity test_bench is
end entity test_bench;

architecture test_reg4 of test_bench is

  signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;

begin

  dut : entity work.reg4(behav)
    port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 );

  stimulus : process is
  begin
    d0 <= '1';  d1 <= '1';  d2 <= '1';  d3 <= '1';
    en <= '0';  clk <= '0';
    wait for 20 ns;
    en <= '1';  wait for 20 ns;
    clk <= '1';  wait for 20 ns;
    d0 <= '0';  d1 <= '0';  d2 <= '0';  d3 <= '0';  wait for 20 ns;
    en <= '0';  wait for 20 ns;
    ...
    wait;
  end process stimulus;

end architecture test_reg4;

----------------------------------------------------------------
-- 1.4.5 Analysis, Elaboration and Execution
----------------------------------------------------------------

----------------------------------------------------------------
-- 1.5 Learning a New Language: Lexical Elements and Syntax
----------------------------------------------------------------

----------------------------------------------------------------
-- 1.5.1 Lexical Elements
----------------------------------------------------------------

----------------------------------------------------------------
-- Comments
----------------------------------------------------------------

----------------------------------------------------------------
-- Identifiers
----------------------------------------------------------------

----------------------------------------------------------------
-- Reserved Words
----------------------------------------------------------------

----------------------------------------------------------------
-- Special Symbols
----------------------------------------------------------------

----------------------------------------------------------------
-- Numbers
----------------------------------------------------------------

----------------------------------------------------------------
-- Characters
----------------------------------------------------------------

----------------------------------------------------------------
-- Strings
----------------------------------------------------------------

----------------------------------------------------------------
-- Bit Strings
----------------------------------------------------------------

----------------------------------------------------------------
-- 1.5.2 Syntax Descriptions
----------------------------------------------------------------

----------------------------------------------------------------
-- Exercises
----------------------------------------------------------------

-- Exercise 2

apply_transform : process is
begin
  d_out <= transform(d_in) after 200 ps;
  debug_test <= transform(d_in);
  wait on enable, d_in;
end process apply_transform;