----------------------------------------------------------------
-- Chapter 5 Basic Modeling Constructs
----------------------------------------------------------------

----------------------------------------------------------------
-- 5.1 Entity Declarations and Architecture Bodies
----------------------------------------------------------------

-- Page 138

entity adder is
  port ( a : in word;
         b : in word;
         sum : out word );
end entity adder;

entity adder is
  port ( a, b : in word;
         sum : out word );
end entity adder;

entity SR_latch is
  port ( S, R : in bit; Q, Q_n : buffer bit );
end entity SR_latch;

-- Page 139

entity and_or_inv is
  port ( a1, a2, b1, b2 : in bit := '1';
         y : out bit );
end entity and_or_inv;

entity top_level is
end entity top_level;

-- Example 5.1, Page 139

entity program_ROM is
  port ( address : in std_ulogic_vector(14 downto 0);
         data : out std_ulogic_vector(7 downto 0);
         enable : in std_ulogic );

  subtype instruction_byte is bit_vector(7 downto 0);
  type program_array is
         array (0 to 2**14 - 1) of instruction_byte;
  constant program : program_array
    := ( X"32", X"3F", X"03",  -- LDA  $3F03
         X"71", X"23",         -- BLT    $23
         ...
       );

end entity program_ROM;

----------------------------------------------------------------
-- 5.1.1 Concurrent Statements
----------------------------------------------------------------

-- Page 141

architecture abstract of adder is
begin

  add_a_b : process (a, b) is
  begin
    sum <= a + b;
  end process add_a_b;

end architecture abstract;

----------------------------------------------------------------
-- 5.1.2 Signal Declarations
----------------------------------------------------------------

-- Example 5.2, Page 142

architecture primitive of and_or_inv is

  signal and_a, and_b : bit;
  signal or_a_b : bit;

begin

  and_gate_a : process (a1, a2) is
  begin
    and_a <= a1 and a2;
  end process and_gate_a;

  and_gate_b : process (b1, b2) is
  begin
    and_b <= b1 and b2;
  end process and_gate_b;

  or_gate : process (and_a, and_b) is
  begin
    or_a_b <= and_a or and_b;
  end process or_gate;

  inv : process (or_a_b) is
  begin
    y <= not or_a_b;
  end process inv;

end architecture primitive;

----------------------------------------------------------------
-- 5.2 Behavioral Descriptions
----------------------------------------------------------------

----------------------------------------------------------------
-- 5.2.1 Signal Assignment
----------------------------------------------------------------

-- Page 143

y <= not or_a_b after 5 ns;

-- Page 144

clk <= '1' after T_pw, '0' after 2*T_pw;

-- Example 5.3, Page 144

clock_gen : process (clk) is
begin
  if not clk then
    clk <= '1' after T_pw, '0' after 2*T_pw;
  end if;
end process clock_gen;

-- Example 5.4, Page 145

mux : process (a, b, sel) is
begin
  case sel is
    when '0' =>
      z <= a after prop_delay;
    when '1' =>
      z <= b after prop_delay;
  end case;
end process mux;

-- Page 145

if device_busy then
  collision_count := collision_count + 1;
  device_req <= unaffected;
else
  accepted_count := accepted_count + 1;
  device_req <= '1';
end if;

----------------------------------------------------------------
-- Conditional Signal Assignments
----------------------------------------------------------------

-- Page 146

reg : process (clk) is
begin
  if rising_edge(clk) then
    q <= (others => '0') when reset else d;
  end if;
end process reg;

if reset then
  q <= (others => '0');
else
  q <= d;
end if;

-- Page 147

req <= '1', '0' after T_fixed when fixed_delay_mode else
       '1', '0' after next_random_delay;

----------------------------------------------------------------
-- Selected Signal Assignments
----------------------------------------------------------------

-- Page 147

with d_sel select
  q <= source0 when "00",
       source1 when "01",
       source2 when "10",
       source3 when "11";

case d_sel is
  when "00" =>
    q <= source0;
  when "01" =>
    q <= source1;
  when "10" =>
    q <= source2;
  when "11" =>
    q <= source3;
end case;

-- Page 148

next_state_logic : process (all) is
begin
  case current_state is
    when idle =>
      next_state <= pending1 when request and busy else
                    active1  when request and not busy else
                    idle;
    when pending1 =>
      ...
    ...
  end case;
end process next_state_logic;

with dut_state select
  dut_req <= '1' when ready,
             '0' when ack,
             unaffected when others;

with request select?
  grant <= "1000" when "1---",
           "0100" when "01--",
           "0010" when "001-",
           "0001" when "0001",
           "0000" when others;

case? request is
  when "1---" =>
    grant <= "1000";
  when "01--" =>
    grant <= "0100";
  when "001-" =>
    grant <= "0010";
  when "0001" =>
    grant <= "0001";
  when others =>
    grant <= "0000";
end case?;

----------------------------------------------------------------
-- 5.2.2 Signal Attributes
----------------------------------------------------------------

-- Page 150

if clk'event and (clk = '1' or clk = 'H')
             and (clk'last_value = '0'
                  or clk'last_value = 'L') then
  assert d'last_event >= Tsu
    report "Timing error: d changed within setup time of clk";
end if;

assert (not clk'event) or clk'delayed'last_event >= Tpw_clk
  report "Clock frequency too high";

-- Example 5.5, Page 150

entity edge_triggered_Dff is
  port ( D : in bit;  clk : in bit;  clr : in bit;
         Q : out bit );
end entity edge_triggered_Dff;

--------------------------------------------------

architecture behavioral of edge_triggered_Dff is
begin

  state_change : process (clk, clr) is
  begin
    if clr then
      Q <= '0' after 2 ns;
    elsif clk'event and clk = '1' then
      Q <= D after 2 ns;
    end if;
  end process state_change;

end architecture behavioral;

-- Page 151

wait until clk;

clk'event and clk

----------------------------------------------------------------
-- 5.2.3 Wait Statements
----------------------------------------------------------------

-- Page 152

half_add : process is
begin
  sum <= a xor b after T_pd;
  carry <= a and b after T_pd;
  wait on a, b;
end process half_add;

half_add : process (a, b) is
begin
  sum <= a xor b after T_pd;
  carry <= a and b after T_pd;
end process half_add;

-- Example 5.6, Page 152

entity mux2 is
  port ( a, b, sel : in bit;
         z : out bit );
end entity mux2;

--------------------------------------------------

architecture behavioral of mux2 is

  constant prop_delay : time := 2 ns;

begin

  slick_mux : process is
  begin
    case sel is
      when '0' =>
        z <= a after prop_delay;
        wait on sel, a;
      when '1' =>
        z <= b after prop_delay;
        wait on sel, b;
    end case;
  end process slick_mux;

end architecture behavioral;

-- Page 153

wait until clk;

-- Example 5.7, Page 153

clock_gen : process is
begin
  clk <= '1' after T_pw, '0' after 2*T_pw;
  wait until not clk;
end process clock_gen;

-- Page 154

wait on clk until not reset;

wait until trigger for 1 ms;

-- Example 5.8, Page 154

clock_gen : process is
begin
  clk <= '1' after T_pw, '0' after 2*T_pw;
  wait for 2*T_pw;
end process clock_gen;

-- Page 154

test_gen : process is
begin
  test0 <= '0' after 10 ns, '1' after 20 ns,
           '0' after 30 ns, '1' after 40 ns;
  test1 <= '0' after 10 ns, '1' after 30 ns;
  wait;
end process test_gen;

----------------------------------------------------------------
-- 5.2.4 Delta Delays
----------------------------------------------------------------

-- Page 155

data <= X"00";

-- Page 156

s <= '1';
...
if s then ...

-- Example 5.9, Page 156

architecture abstract of computer_system is

  subtype word is bit_vector(31 downto 0);

  signal address : natural;
  signal read_data, write_data : word;
  signal mem_read, mem_write : bit := '0';
  signal mem_ready : bit := '0';

begin

  cpu : process is
    variable instr_reg : word;
    variable PC : natural;
    ...    -- other declarations
  begin
    loop
      address <= PC;
      mem_read <= '1';
      wait until mem_ready;
      instr_reg := read_data;
      mem_read <= '0';
      wait until not mem_ready;
      PC := PC + 4;
      ...    -- execute the instruction
    end loop;
  end process cpu;

  memory : process is
    type memory_array is array (0 to 2**14 - 1) of word;
    variable store : memory_array := ( ... );
  begin
    wait until mem_read or mem_write;
    if mem_read then
      read_data <= store( address / 4 );
      mem_ready <= '1';
      wait until not mem_read;
      mem_ready <= '0';
    else
      ...    -- perform write access
    end if;
  end process memory;

end architecture abstract;

----------------------------------------------------------------
-- 5.2.5 Transport and Inertial Delay Mechanisms
----------------------------------------------------------------

-- Page 158

transmission_line : process (line_in) is
begin
  line_out <= transport line_in after 500 ps;
end process transmission_line;

-- Example 5.10, Page 159

asym_delay : process (a) is
  constant Tpd_01 : time := 800 ps;
  constant Tpd_10 : time := 500 ps;
begin
  if a then
    z <= transport a after Tpd_01;
  else  -- not a
    z <= transport a after Tpd_10;
  end if;
end process asym_delay;

-- Page 160

inv : process (a) is
begin
  y <= inertial not a after 3 ns;
end process inv;

-- Page 161

inv : process (a) is
begin
  y <= reject 2 ns inertial not a after 3 ns;
end process inv;

-- Page 162

s <= reject 5 ns inertial '1' after 8 ns;

-- Example 5.11, Page 163

library ieee;  use ieee.std_logic_1164.all;

entity and2 is
  port ( a, b : in std_ulogic;  y : out std_ulogic );
end entity and2;

--------------------------------------------------

architecture detailed_delay of and2 is

  signal result : std_ulogic;

begin

  gate : process (a, b) is
  begin
    result <= a and b;
  end process gate;

  delay : process (result) is
  begin
    if result then
      y <= reject 400 ps inertial '1' after 1.5 ns;
    elsif not result then
      y <= reject 300 ps inertial '0' after 1.2 ns;
    else
      y <= reject 300 ps inertial 'X' after 500 ps;
    end if;
  end process delay;

end architecture detailed_delay;

-- Page 163

wire_out <= transport
  wire_in after T_wire_delay when delay_mode = fixed else
  wire_in after delay_lookup("wire_out");

with speed_grade select
  z <= reject Tpr inertial
    result after Tpd_std when std_grade,
    result after Tpd_fast when fast_grade,
    result after Tpd_redhot when redhot_grade;

----------------------------------------------------------------
-- 5.2.6 Process Statements
----------------------------------------------------------------

-- Example 5.12, Page 165

next_state_logic : process (all) is
begin
  out1 <= '0'; out2 <= '0'; ...
  case current_state is
    when idle =>
      out1 <= '1';
      if in1 and not in2 then
        out2 <= '1';
        next_state <= busy1;
      elsif in1 and in2 then
        next_state <= busy2;
      else
        next_state <= idle;
      end if;
    ...
  end case;
end process next_state_logic;

----------------------------------------------------------------
-- 5.2.7 Concurrent Signal Assignment Statements
----------------------------------------------------------------

----------------------------------------------------------------
-- Concurrent Simple Signal Assignments
----------------------------------------------------------------

-- Page 166

PC_incr : next_PC <= PC + 4 after 5 ns;

PC_incr : process is
begin
  next_PC <= PC + 4 after 5 ns;
  wait on PC;
end process PC_incr;

-- Example 5.13, Page 167

entity Dff is
  port ( clk, d : in bit; q, q_n : out bit );
end entity Dff;

--------------------------------------------------

architecture rtl of Dff is
begin
  ff : process (clk) is
  begin
    if clk then
      q <= d;
    end if;
  end process ff;
  q_n <= not q;
end architecture rtl;

----------------------------------------------------------------
-- Concurrent Conditional Signal Assignment
----------------------------------------------------------------

-- Example 5.14, Page 167

zmux : z <= d0 when not sel1 and not sel0 else
            d1 when not sel1 and     sel0 else
            d2 when     sel1 and not sel0 else
            d3 when     sel1 and     sel0;

zmux : process is
begin
  if not sel1 and not sel0 then
    z <= d0;
  elsif not sel1 and sel0 then
    z <= d1;
  elsif sel1 and not sel0 then
    z <= d2;
  elsif sel1 and sel0 then
    z <= d3;
  end if;
  wait on d0, d1, d2, d3, sel0, sel1;
end process zmux;

-- Example 5.14, Page 168

zmux : z <= d0 when not sel1 and not sel0 else
            d1 when not sel1 and     sel0 else
            d2 when     sel1 and not sel0 else
            d3;

zmux : process is
begin
  if not sel1 and not sel0 then
    z <= d0;
  elsif not sel1 and sel0 then
    z <= d1;
  elsif sel1 and not sel0 then
    z <= d2;
  else
    z <= d3;
  end if;
  wait on d0, d1, d2, d3, sel0, sel1;
end process zmux;

-- Example 5.15, Page 169

reset_gen : reset <= '1', '0' after 200 ns when extended_reset else
                     '1', '0' after 50 ns;

reset_gen : process is
begin
  if extended_reset then
    reset <= '1', '0' after 200 ns;
  else
    reset <= '1', '0' after 50 ns;
  end if;
  wait;
end process reset_gen;

-- Page 169

asym_delay : z <= transport a after Tpd_01 when a else
                            a after Tpd_10;

-- Example 5.16, Page 169

scheduler :
  request <=
    first_priority_request after scheduling_delay
      when priority_waiting and server_status = ready else
    first_normal_request after scheduling_delay
      when not priority_waiting and server_status = ready else
    unaffected
      when server_status = busy else
    reset_request after scheduling_delay;

-- Example 5.16, Page 170

scheduler : process is
begin
  if priority_waiting and server_status = ready then
    request <= first_priority_request after scheduling_delay;
  elsif not priority_waiting and server_status = ready then
    request <= first_normal_request after scheduling_delay;
  elsif server_status = busy then
    null;
  else
    request <= reset_request after scheduling_delay;
  end if;
  wait on first_priority_request, priority_waiting,
          server_status, first_normal_request, reset_request;
end process scheduler;

----------------------------------------------------------------
-- Concurrent Selected Signal Assignments
----------------------------------------------------------------

-- Example 5.17, Page 171

alu : with alu_function select
        result <= a + b after Tpd   when alu_add |
                                         alu_add_unsigned,
                  a - b after Tpd   when alu_sub |
                                         alu_sub_unsigned,
                  a and b after Tpd when alu_and,
                  a or b after Tpd  when alu_or,
                  a after Tpd       when alu_pass_a;

alu : process is
begin
  case alu_function is
    when alu_add |
         alu_add_unsigned =>  result <= a + b after Tpd;
    when alu_sub |
         alu_sub_unsigned =>  result <= a - b after Tpd;
    when alu_and          =>  result <= a and b after Tpd;
    when alu_or           =>  result <= a or b after Tpd;
    when alu_pass_a       =>  result <= a after Tpd;
  end case;
  wait on alu_function, a, b;
end process alu;

-- Example 5.18, Page 172

entity full_adder is
  port ( a, b, c_in : bit;  s, c_out : out bit );
end entity full_adder;

--------------------------------------------------

architecture truth_table of full_adder is
begin

  with bit_vector'(a, b, c_in) select
    (c_out, s) <= bit_vector'("00") when "000",
                  bit_vector'("01") when "001",
                  bit_vector'("01") when "010",
                  bit_vector'("10") when "011",
                  bit_vector'("01") when "100",
                  bit_vector'("10") when "101",
                  bit_vector'("10") when "110",
                  bit_vector'("11") when "111";

end architecture truth_table;

-- Page 172

with request select?
  grant <= "1000" when "1---",
           "0100" when "01--",
           "0010" when "001-",
           "0001" when "0001",
           "0000" when others;

----------------------------------------------------------------
-- 5.2.8 Concurrent Assertion Statements
----------------------------------------------------------------

-- Example 5.19, Page 173

entity S_R_flipflop is
  port ( s, r : in bit;  q, q_n : out bit );
end entity S_R_flipflop;

--------------------------------------------------

architecture functional of S_R_flipflop is

begin

  q <= '1' when s else
       '0' when r;

  q_n <= '0' when s else
         '1' when r;

  check : assert not (s and r)
            report "Incorrect use of S_R_flip_flop: " &
                   "s and r both '1'";

end architecture functional;

-- Example 5.19, Page 174

check : process is
begin
  assert not (s and r)
    report "Incorrect use of S_R_flip_flop: " &
           "s and r both '1'";
  wait on s, r;
end process check;

----------------------------------------------------------------
-- 5.2.9 Entities and Passive Processes
----------------------------------------------------------------

-- Example 5.20, Page 175

entity S_R_flipflop is
  port ( s, r : in bit;  q, q_n : out bit );

begin

  check : assert not (s and r)
            report "Incorrect use of S_R_flip_flop: " &
                   "s and r both '1'";

end entity S_R_flipflop;

-- Example 5.21, Page 175

entity ROM is
  port ( address : in natural;
         data : out bit_vector(0 to 7);
         enable : in bit );

begin

  trace_reads : process (enable) is
  begin
    if enable then
      report "ROM read at time " & to_string(now)
             & " from address " & to_string(address);
    end if;
  end process trace_reads;

end entity ROM;

----------------------------------------------------------------
-- 5.3 Structural Descriptions
----------------------------------------------------------------

-- Page 176

entity DRAM_controller is
  port ( rd, wr, mem : in bit;
         ras, cas, we, ready : out bit  );
end entity DRAM_controller;

-- Page 177

main_mem_controller : entity work.DRAM_controller(fpld)
  port map ( cpu_rd, cpu_wr, cpu_mem,
             mem_ras, mem_cas, mem_we, cpu_rdy );

main_mem_controller : entity work.DRAM_controller(fpld)
  port map ( rd => cpu_rd, wr => cpu_wr,
             mem => cpu_mem, ready => cpu_rdy,
             ras => mem_ras, cas => mem_cas, we => mem_we );

-- Example 5.22, Page 177

entity reg4 is
  port ( clk, clr, d0, d1, d2, d3 : in bit;
         q0, q1, q2, q3 : out bit );
end entity reg4;

----------------------------------------------

architecture struct of reg4 is
begin

  bit0 : entity work.edge_triggered_Dff(behavioral)
    port map (d0, clk, clr, q0);
  bit1 : entity work.edge_triggered_Dff(behavioral)
    port map (d1, clk, clr, q1);
  bit2 : entity work.edge_triggered_Dff(behavioral)
    port map (d2, clk, clr, q2);
  bit3 : entity work.edge_triggered_Dff(behavioral)
    port map (d3, clk, clr, q3);

end architecture struct;

-- Example 5.22, Page 179

subtype digit is bit_vector(3 downto 0);

entity counter is
  port ( clk, clr : in bit;
         q0, q1 : out digit );
end entity counter;

--------------------------------------------------

architecture registered of counter is

  signal current_val0, current_val1, next_val0, next_val1 : digit;

begin

  val0_reg : entity work.reg4(struct)
    port map ( d0 => next_val0(0), d1 => next_val0(1),
               d2 => next_val0(2), d3 => next_val0(3),
               q0 => current_val0(0), q1 => current_val0(1),
               q2 => current_val0(2), q3 => current_val0(3),
               clk => clk, clr => clr );

  val1_reg : entity work.reg4(struct)
    port map ( d0 => next_val1(0), d1 => next_val1(1),
               d2 => next_val1(2), d3 => next_val1(3),
               q0 => current_val1(0), q1 => current_val1(1),
               q2 => current_val1(2), q3 => current_val1(3),
               clk => clk, clr => clr );

  incr0 : entity work.add_1(boolean_eqn) ...;

  incr1 : entity work.add_1(boolean_eqn) ...;

  buf0 : entity work.buf4(basic) ...;

  buf1 : entity work.buf4(basic) ...;

end architecture registered;

-- Page 180

type FIFO_status is record
    nearly_full, nearly_empty, full, empty : bit;
  end record FIFO_status;

DMA_buffer : entity work.FIFO
  port map ( ..., 
             status.nearly_full => start_flush,
             status.nearly_empty => end_flush,
             status.full => DMA_buffer_full,
             status.empty => DMA_buffer_empty, ... );

-- Example 5.23, Page 180

entity reg is
  port ( d : in bit_vector(7 downto 0);
         q : out bit_vector(7 downto 0);
         clk : in bit );
end entity reg;

-- Example 5.23, Page 181

architecture RTL of microprocessor is

  signal interrupt_req : bit;
  signal interrupt_level : bit_vector(2 downto 0);
  signal carry_flag, negative_flag,
         overflow_flag, zero_flag : bit;
  signal program_status : bit_vector(7 downto 0);
  signal clk_PSR : bit;
  ...

begin

  PSR : entity work.reg
    port map ( d(7) => interrupt_req,
               d(6 downto 4) => interrupt_level,
               d(3) => carry_flag,     d(2) => negative_flag,
               d(1) => overflow_flag,  d(0) => zero_flag,
               q => program_status,
               clk => clk_PSR );
  ...

end architecture RTL;

-- Page 181

entity and_gate is
  port ( i : in bit_vector;  y : out bit );
end entity and_gate;

signal serial_select, write_en, bus_clk, serial_wr : bit;

-- Page 182

serial_write_gate : entity work.and_gate
  port map ( i(1) => serial_select,
             i(2) => write_en,
             i(3) => bus_clk,
             y => serial_wr );

type bv_pair is array (1 to 2) of bit_vector;

entity ent3 is
  port ( p : in bv_pair );
end entity ent3;

signal s1, s2 : bit;
signal sv1, sv2 : bit_vector(4 to 7);
...

inst3 : entity work.ent3
  port map ( p(1)(0) => s1, p(1)(1 to 4) => sv1,
             p(2)(0) => s2, p(2)(1 to 4) => sv2 );

signal s1, s2 : bit;
signal sv1, sv2 : bit_vector(4 to 7);
...

inst3 : entity work.ent3
  port map ( p(1)(0) => s1, p(1)(1 to 4) => sv1,
             p(2)(15) => s2, p(2)(11 to 14) => sv2 ); -- illegal

-- Example 5.24, Page 183

entity mux4 is
  port ( i0, i1, i2, i3, sel0, sel1 : in bit;
         z : out bit );
end entity mux4;

a_mux : entity work.mux4
  port map ( sel0 => select_line, i0 => line0, i1 => line1,
             z => result_line,
             sel1 => '0', i2 => '1', i3 => '1' );

-- Example 5.25, Page 184

io_ctrl_1 : entity work.io_controller(rtl)
  port map ( en => rd_en and io_sel and addr ?= io_base,
             ... );

signal en_tmp : std_ulogic;
...

en_tmp <= rd_en and io_sel and addr ?= io_base;

io_ctrl_1 : entity work.io_controller(rtl)
  port map ( en => en_tmp,
             ... );

-- Example 5.26, Page 184

entity and_or_inv is
  port ( a1, a2, b1, b2 : in bit := '1';
         y : out bit );
end entity and_or_inv;

f_cell : entity work.and_or_inv
  port map ( a1 => A, a2 => B, b1 => C, b2 => open, y => F );

-- Page 185

entity and3 is
  port ( a, b, c : in bit := '1';
         z, not_z : out bit);
end entity and3;

g1 : entity work.and3 port map ( a => s1, b => s2, not_z => ctrl1 );

g1 : entity work.and3 port map ( a => s1, b => s2, not_z => ctrl1,
                                 c => open, z => open );

-- Page 186

signal tied_0 : bit := '0';
signal tied_1 : bit := '1';

port map ( sel0 => select_line, i0 => line0, i1 => line1,
           z => result_line,
           sel1 => tied_0, i2 => tied_1, i3 => tied_1 );

----------------------------------------------------------------
-- 5.4 Design Processing
----------------------------------------------------------------

----------------------------------------------------------------
-- 5.4.1 Analysis
----------------------------------------------------------------

----------------------------------------------------------------
-- 5.4.2 Design Libraries and Contexts
----------------------------------------------------------------

-- Example 5.28, Page 189

library widget_cells, wasp_lib;

architecture cell_based of filter is

  -- declaration of signals, etc
  ...

begin

  clk_pad : entity wasp_lib.in_pad
    port map ( i => clk, z => filter_clk );

  accum : entity widget_cells.reg32
    port map ( en => accum_en, clk => filter_clk, d => sum,
               q => result );

  alu : entity work.adder
    port map ( a => alu_op1, b => alu_op2, y => sum, c => carry );

  -- other component instantiations
  ...

end architecture cell_based;

-- Page 190

library widget_cells, wasp_lib;

use widget_cells.reg32;

accum : entity reg32
  port map ( en => accum_en, clk => filter_clk, d => sum,
             q => result );

use wasp_lib.all;

----------------------------------------------------------------
-- Context Declarations
----------------------------------------------------------------

-- Example 5.29, Page 191

context widget_context is
  library ieee;
  use ieee.std_logic_1164.all;
  use widget_lib.all;
end context widget_context;

library widget_lib;
context widget_lib.widget_context;
entity sample is
  ...
end entity sample;

context dongle_context is
library widget_lib;
context widget_lib.widget_context;
  library gizmo_IP_lib;
  use gizmo_IP_lib.all;
  use dongle_lib.all;
end context dongle_context;

-- Example 5.29, Page 192

library dongle_lib;
context dongle_lib.dongle_context;
entity frobber is
  ...
end entity frobber;

library dongle_lib;
library widget_lib;
library ieee;
use ieee.std_logic_1164.all;
use widget_lib.all;
library gizmo_IP_lib;
use gizmo_IP_lib.all;
use dongle_lib.all;
entity frobber is
  ...
end entity frobber;

-- Page 192

library fizz_lib; -- Illegal: precedes context declaration
context frazzle_ctx is
  use fizz_lib.fizz_pkg.all;
end context frazzle_ctx;

----------------------------------------------------------------
-- 5.4.3 Elaboration
----------------------------------------------------------------

----------------------------------------------------------------
-- 5.4.4 Execution
----------------------------------------------------------------

----------------------------------------------------------------
-- Exercises
----------------------------------------------------------------

-- Exercise 3

process is
begin
  s <= 'Z', '0' after 10 ns, '1' after 30 ns;
  wait for 50 ns;
  s <= '1' after 5 ns; 'H' after 15 ns;
  wait for 50 ns;
  s <= 'Z';
  wait;
end process;

-- Exercise 7

s <= '1';
v1 := s = '1';
wait on s;
v2 := s = '1';

-- Exercise 8

z <= transport '1' after 6 ns;
wait for 3 ns;
z <= transport '0' after 4 ns;
wait for 5 ns;
z <= transport '1' after 6 ns;
wait for 1 ns;
z <= transport '0' after 4 ns;

-- Exercise 9

x <= reject 5 ns inertial 1 after 7 ns,
                         23 after 9 ns,
                          5 after 10 ns,
                         23 after 12 ns,
                         -5 after 15 ns;
wait for 6 ns;
x <= reject 5 ns inertial 23 after 7 ns;

-- Exercise 10

logic_block : process (all) is
begin
  out1 <= '0'; out2 <= '0';
  case current_state is
    when s0 => if in1 then
                 next_state <= s1;
                 out1 <= '1';
               else
                 next_state <= idle;
               end if;
    when s1 => next_state <= s2;
               out2 <= '1';
    when s2 => next_state <= idle;
  end case;
end process logic_block;

-- Exercise 11

mux_logic :
  z <= a and not b after 5 ns
         when enable and not sel else
       x or y after 6 ns
         when enable and sel else
       '0' after 4 ns;

-- Exercise 12

with bit_vector'(s, r) select
  q <= unaffected when "00",
       '0' when "01",
       '1' when "10" | "11";

-- Exercise 15

decode_1 : entity work.ttl_74x138(basic)
  port map ( c => a(2), b => a(1), a => a(0),
             g1 => a(3), g2a_n => sel_n, g2b_n => '0',
             y7_n => en_n(15), y6_n => en_n(14),
             y5_n => en_n(13), y4_n => en_n(12),
             y3_n => en_n(11), y2_n => en_n(10),
             y1_n => en_n(9), y0_n => en_n(8) );

decode_0 : entity work.ttl_74x138(basic)
  port map ( c => a(2), b => a(1), a => a(0),
             g1 => '1', g2a_n => sel_n, g2b_n => a(3),
             y7_n => en_n(7), y6_n => en_n(6),
             y5_n => en_n(5), y4_n => en_n(4),
             y3_n => en_n(3), y2_n => en_n(2),
             y1_n => en_n(1), y0_n => en_n(0) );

-- Exercise 20

entity counter is
  port ( clk_n, load_en : in std_ulogic;
         d : in std_ulogic_vector(3 downto 0);
         q : out std_ulogic_vector(3 downto 0) );
end entity counter;

-- Exercise 23

entity adder is
  port ( a, b : in integer; s : out integer );
end entity adder;

-- Exercise 25

producer : process is
  variable next_data : natural := 0;
begin
  data <= next_data; next_data := next_data + 1;
  data_ready <= '1';
  wait until data_ack;
  data_ready <= '0';
  wait until not data_ack;
end process producer;

-- Exercise 26

entity delay_line is
  port ( input : in std_ulogic;
         output : out std_ulogic_vector );
end entity delay_line;

-- Exercise 32

entity d_latch is
  port ( latch_en, out_en, d : in std_ulogic;
         q : out std_ulogic );
end entity d_latch;

-- Exercise 34

entity arbiter is
  port ( request : in bit_vector(0 to 3);
         acknowledge : out bit_vector(0 to 3) );
end entity arbiter;

-- Exercise 37

entity carry_look_ahead_generator is
  port ( p0, p1, p2, p3, g0, g1, g2, g3 : in bit;
         c_in : in bit; c1, c2, c3 : out bit );
end entity carry_look_ahead_generator;