----------------------------------------------------------------
-- Chapter 8 Resolved Signals
----------------------------------------------------------------

----------------------------------------------------------------
-- 8.1 Basic Resolved Signals
----------------------------------------------------------------

-- Page 267

type tri_state_logic is ('0', '1', 'Z');

-- Page 268

type tri_state_logic_array is
  array (integer range <>) of tri_state_logic;

function resolve_tri_state_logic
  ( values : in tri_state_logic_array )
  return tri_state_logic is
  variable result : tri_state_logic := 'Z';
begin
  for index in values'range loop
    if values(index) /= 'Z' then
      result := values(index);
    end if;
  end loop;
  return result;
end function resolve_tri_state_logic;

signal s1 : resolve_tri_state_logic tri_state_logic;

-- Page 269

subtype resolved_logic is
  resolve_tri_state_logic tri_state_logic;

signal s2, s3 : resolved_logic;

-- Example 8.1, Page 269

package MVL4 is

  -- unresolved logic type
  type MVL4_ulogic is ('X', '0', '1', 'Z');

  type MVL4_ulogic_vector is
    array (natural range <>) of MVL4_ulogic;

  function resolve_MVL4
    ( contribution : MVL4_ulogic_vector ) return MVL4_ulogic;

  subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;

  function "not" ( r : MVL4_ulogic ) return MVL4_ulogic;
  function "and" ( l, r : MVL4_ulogic ) return MVL4_ulogic;
  function "or"  ( l, r : MVL4_ulogic ) return MVL4_ulogic;
  ...

  function to_X01 ( a : MVL4_ulogic ) return MVL4_ulogic;

  function "??" ( r : MVL4_ulogic ) return boolean;

end package MVL4;

--------------------------------------------------

package body MVL4 is

  type table is
    array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;

  constant resolution_table : table :=
    --  'X'  '0'  '1'  'Z'
    --  ------------------
    ( ( 'X', 'X', 'X', 'X' ),    -- 'X'
      ( 'X', '0', 'X', '0' ),    -- '0'
      ( 'X', 'X', '1', '1' ),    -- '1'
      ( 'X', '0', '1', 'Z' ) );  -- 'Z'

  function resolve_MVL4 ( contribution : MVL4_ulogic_vector )
                        return MVL4_ulogic is
    variable result : MVL4_ulogic := 'Z';
  begin
    for index in contribution'range loop
      result := resolution_table(result, contribution(index));
    end loop;
    return result;
  end function resolve_MVL4;

  function "not" ( r : MVL4_ulogic ) return MVL4_ulogic is
  begin
    case r is
      when '1' => return '0';
      when '0' => return '1';
      when others => return 'X';
    end case;
  end function "not";

  function "and" ( l, r : MVL4_ulogic ) return MVL4_ulogic is ...
                                                              
  function "or"  ( l, r : MVL4_ulogic ) return MVL4_ulogic is ...

  ...

  function to_X01 ( a : MVL4_ulogic ) return MVL4_ulogic is
  begin
    case a is
      when '0' | '1' => return a;
      when 'X' | 'Z' => return 'X';
    end case;
  end function to_X01;

  function "??" ( r : MVL4_ulogic ) return boolean is
  begin
    return r = '1';
  end function "??";

end package body MVL4;

-- Example 8.1, Page 271

use work.MVL4.all;

entity tri_state_buffer is
  port ( a, enable : in MVL4_ulogic;  y : out MVL4_ulogic );
end entity tri_state_buffer;

--------------------------------------------------

architecture behavioral of tri_state_buffer is
begin

  y <= to_X01(a) when enable else
       'Z'       when not enable else
       'X';

end architecture behavioral;

-- Example 8.1, Page 272

use work.MVL4.all;

architecture gate_level of misc_logic is

  signal src1, src1_enable : MVL4_ulogic;
  signal src2, src2_enable : MVL4_ulogic;
  signal selected_val : MVL4_logic;
  ...

begin

  src1_buffer : entity work.tri_state_buffer(behavioral)
    port map ( a => src1, enable => src1_enable,
               y => selected_val );

  src2_buffer : entity work.tri_state_buffer(behavioral)
    port map ( a => src2, enable => src2_enable,
               y => selected_val );

  ...

end architecture gate_level;

----------------------------------------------------------------
-- 8.1.1 Composite Resolved Subtypes
----------------------------------------------------------------

-- Example 8.2, Page 272

package words is

  type X01Z is ('X', '0', '1', 'Z');
  type uword is array (natural range <>) of X01Z;

  type uword_vector is array (natural range <>) of uword;

  function resolve_word
    ( contribution : uword_vector ) return uword;

  subtype word is resolve_word uword;

end package words;

--------------------------------------------------

package body words is

  type table is array (X01Z, X01Z) of X01Z;

  constant resolution_table : table :=
    --  'X'  '0'  '1'  'Z'
    --  ------------------
    ( ( 'X', 'X', 'X', 'X' ),    -- 'X'
      ( 'X', '0', 'X', '0' ),    -- '0'
      ( 'X', 'X', '1', '1' ),    -- '1'
      ( 'X', '0', '1', 'Z' ) );  -- 'Z'

  function resolve_word
    ( contribution : uword_vector ) return uword is
    variable result : uword(contribution'element'range)
               := (others => 'Z');
  begin
    for index in contribution'range loop
      for element in result'range loop
        result(element) :=
          resolution_table( result(element),
                            contribution(index)(element) );
      end loop;
    end loop;
    return result;
  end function resolve_word;

end package body words;

-- Example 8.2, Page 273

use work.words.all;

entity cpu is
  port ( address : out uword(23 downto 0);
         data : inout uword(31 downto 0);  ... );
end entity cpu;

--------------------------------------------------

use work.words.all;

entity memory is
  port ( address : in uword(23 downto 0);
         data : inout uword(31 downto 0); ... );
end entity memory;

-- Example 8.2, Page 274

architecture top_level of computer_system is

  use work.words.all;

  signal address : uword(23 downto 0);
  signal data : word(31 downto 0);
  ...

begin

  the_cpu : entity work.cpu(behavioral)
    port map ( address, data, ... );

  the_memory : entity work.memory(behavioral)
    port map ( address, data, ... );

  ...

end architecture top_level;

-- Page 274

boot_rom : entity work.ROM(behavioral)
  port map ( a => address, d => data(24 to 31), ... );  -- illegal

-- Page 275

type MVL4_logic_vector is array (natural range <>) of MVL4_logic;

subtype MVL4_logic_vector is (resolve_MVL4) std_ulogic_vector;

subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;

type unresolved_RAM_content_type is
  array (natural range <>) of MVL4_ulogic_vector;

-- Page 276

subtype RAM_content_type is
  ((resolve_MVL4)) unresolved_RAM_content_type;

type unresolved_status_type is record
  valid : MVL4_ulogic;
  dirty : MVL4_ulogic;
  tag : MVL4_ulogic_vector;
end record unresolved_status_type;

subtype status_resolved_valid is
  (valid wired_and) unresolved_status_type;

subtype status_resolved_flags is
  (valid wired_and, dirty wired_or) unresolved_status_type;

subtype status_resolved_tag is
  (tag(resolve_MVL4)) unresolved_status_type;

subtype resolved_status_type is
  ( tag(resolve_MVL4),
    valid wired_and,
    dirty wired_or ) unresolved_status_type;

-- Example 8.3, Page 277

use work.MVL4.all;

entity ROM is
  port ( a : in MVL4_ulogic_vector(15 downto 0);
         d : out MVL4_ulogic_vector(7 downto 0);
         rd : in MVL4_ulogic );
end entity ROM;

--------------------------------------------------

use work.MVL4.all;

entity SIMM is
  port ( a : in MVL4_ulogic_vector(9 downto 0);
         d : inout MVL4_ulogic_vector(31 downto 0);
         ras, cas, we, cs : in MVL4_ulogic );
end entity SIMM;

architecture detailed of memory_subsystem is

  signal internal_data : MVL4_logic_vector(31 downto 0);
  ...

begin

  boot_ROM : entity work.ROM(behavioral)
    port map ( a => internal_addr(15 downto 0),
               d => internal_data(7 downto 0),
               rd => ROM_select );

  main_mem : entity work.SIMM(behavioral)
    port map ( a => main_mem_addr, d => internal_data, ... );

  ...

end architecture detailed;

----------------------------------------------------------------
-- 8.1.2 Summary of Resolved Subtypes
----------------------------------------------------------------

-- Page 278

type small_int is range 1 to 4;
type small_array is array (small_int range <>) of ... ;

----------------------------------------------------------------
-- 8.1.3 IEEE std_logic_1164 Resolved Subtypes
----------------------------------------------------------------

-- Page 278

type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');

type std_ulogic_vector is array ( natural range <> ) of std_ulogic;

function resolved ( s : std_ulogic_vector ) return std_ulogic;

-- Page 279

subtype std_logic is resolved std_ulogic;

subtype std_logic_vector (resolved) std_ulogic_vector;

type stdlogic_table is array (std_ulogic, std_ulogic) of std_ulogic;
constant resolution_table : stdlogic_table :=
  -- ---------------------------------------------
  -- 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'
  -- ---------------------------------------------
  ( ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ),  -- 'U'
    ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ),  -- 'X'
    ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ),  -- '0'
    ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ),  -- '1'
    ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ),  -- 'Z'
    ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ),  -- 'W'
    ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ),  -- 'L'
    ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ),  -- 'H'
    ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' )   -- '-'
  );

function resolved ( s : std_ulogic_vector ) return std_ulogic is
  variable result : std_ulogic := 'Z'; -- weakest state default
begin
  if s'length = 1 then
    return s(s'low);
  else
    for i in s'range loop
      result := resolution_table(result, s(i));
    end loop;
  end if;
  return result;
end function resolved;

-- Page 280

subtype X01 is
  resolved std_ulogic range 'X' to '1'; -- ('X','0','1')
subtype X01Z is
  resolved std_ulogic range 'X' to 'Z'; -- ('X','0','1','Z')
subtype UX01 is
  resolved std_ulogic range 'U' to '1'; -- ('U','X','0','1')
subtype UX01Z is
  resolved std_ulogic range 'U' to 'Z'; -- ('U','X','0','1','Z')

----------------------------------------------------------------
-- 8.2 Resolved Signals, Ports, and Parameters
----------------------------------------------------------------

-- Example 8.4, Page 281

library ieee;  use ieee.std_logic_1164.all;

entity bus_module is
  port ( synch : inout std_ulogic;  ... );
end entity bus_module;

architecture top_level of bus_based_system is

  signal synch_control : std_logic;
  ...

begin

  synch_control_pull_up : synch_control <= 'H';

  bus_module_1 : entity work.bus_module(behavioral)
    port map ( synch => synch_control, ... );

  bus_module_2 : entity work.bus_module(behavioral)
    port map ( synch => synch_control, ... );

  ...

end architecture top_level;

architecture behavioral of bus_module is
begin

  behavior : process is
    ...
  begin
    synch <= '0'  after Tdelay_synch;
    ...
    -- ready to start operation
    synch <= 'Z' after Tdelay_synch;
    wait until synch = 'H';
    -- proceed with operation
    ...
  end process behavior;

end architecture behavioral;

----------------------------------------------------------------
-- 8.2.1 Resolved Ports
----------------------------------------------------------------

-- Page 282

library ieee;  use ieee.std_logic_1164.all;

entity IO_section is
  port ( data_ack : inout std_logic;  ... );
end entity IO_section;

-- Example 8.5, Page 282

library ieee; use ieee.std_logic_1164.all;
entity memory_256Kx8 is
  port ( ce_n, oe_n, we_n : in std_ulogic;
         a : in std_ulogic_vector(17 downto 0);
         d : inout std_ulogic_vector(7 downto 0) );
end entity memory_256Kx8;

-- Example 8.5, Page 283

library ieee; use ieee.std_logic_1164.all;
entity memory_1Mx8 is
  port ( ce_n, oe_n, we_n : in std_ulogic;
         a : in std_ulogic_vector(19 downto 0);
         d : inout std_logic_vector(7 downto 0) );
end entity memory_1Mx8;

architecture struct of memory_1Mx8 is
  signal ce_decoded_n : std_ulogic_vector(3 downto 0);
begin

  with a(19 downto 18) select
    ce_decoded_n <= "1110" when "00",
                    "1101" when "01",
                    "1011" when "10",
                    "0111" when "11",
                    "XXXX" when others;

  chip0 : component memory_256Kx8
    port map ( ce_n => ce_decoded_n(0),
               oe_n => oe_n, we_n => we_n,
               a => a(17 downto 0), d => d );

  chip1 : component memory_256Kx8
    port map ( ce_n => ce_decoded_n(1),
               oe_n => oe_n, we_n => we_n,
               a => a(17 downto 0), d => d );

  ...

end architecture struct;

-- Example 8.7, Page 285

entity device is
  port ( en : in std_ulogic;
         d_out : out std_ulogic_vector(7 downto 0); ... );
end entity device;

architecture verifying of device is
  constant T_z : delay_length := 200 ps;
begin
  d_out <= ... when en else
           ... when not en else
           "XXXXXXXX";
  assert en or (not en'delayed(T_z) and d_out ?= "ZZZZZZZZ");
end architecture verifying;

----------------------------------------------------------------
-- 8.2.2 Driving Value Attribute
----------------------------------------------------------------

----------------------------------------------------------------
-- 8.2.3 Resolved Signal Parameters
----------------------------------------------------------------

-- Example 8.8, Page 286

procedure init_synchronize ( signal synch : out std_logic ) is
begin
  synch <= '0';
end procedure init_synchronize;

procedure begin_synchronize ( signal synch : inout std_logic;
                              Tdelay : in delay_length := 0 fs ) is
begin
  synch <= 'Z' after Tdelay;
  wait until synch;
end procedure begin_synchronize;

procedure end_synchronize ( signal synch : inout std_logic;
                            Tdelay : in delay_length := 0 fs ) is
begin
  synch <= '0' after Tdelay;
  wait until not synch;
end procedure end_synchronize;

-- Example 8.8, Page 287

synchronized_module : process is
  ...
begin
  init_synchronize(barrier);
  ...
  loop
    ...
    begin_synchronize(barrier);
    ...    -- perform operation, synchronized with other processes
    end_synchronize(barrier);
    ...
  end loop;
end process synchronized_module;

----------------------------------------------------------------
-- Exercises
----------------------------------------------------------------

-- Exercise 2

signal synch_control : wired_and tri_state_logic := '0';

-- Exercise 3

signal int_req : MVL4_logic;

-- Exercise 6

signal data_bus : MVL4_logic_vector(0 to 15);

data_bus <= "ZZZZZZZZZZZZZZZZ";

data_bus(0 to 7) <= "XXXXZZZZ";

data_bus(8 to 15) <= "00111100";