----------------------------------------------------------------
-- Chapter 9 Predefined and Standard Packages
----------------------------------------------------------------

----------------------------------------------------------------
-- 9.1 The Predefined Packages standard and env
----------------------------------------------------------------

-- Page 293

library std, work; use std.standard.all;

result := std.standard."<" ( a, b );

-- Example 9.1, Page 294

function "<" ( a, b : bit_vector ) return boolean is
  variable tmp1 : bit_vector(a'range) := a;
  variable tmp2 : bit_vector(b'range) := b;
begin
  tmp1(tmp1'left) := not tmp1(tmp1'left);
  tmp2(tmp2'left) := not tmp2(tmp2'left);
  return std.standard."<" ( tmp1, tmp2 );
end function "<";

-- Page 295

procedure stop (status: integer);
procedure stop;

procedure finish (status: integer);
procedure finish;

function resolution_limit return delay_length;

wait for env.resolution_limit;

if env.resolution_limit > ns then -- potentially illegal!
  ... -- do coarse-resolution actions
else
  ... -- do fine-resolution actions
end if;

-- Page 296

if env.resolution_limit > 1.0E-9 sec then
  ... -- do coarse-resolution actions
else
  ... -- do fine-resolution actions
end if;

----------------------------------------------------------------
-- 9.2 IEEE Standard Packages
----------------------------------------------------------------

----------------------------------------------------------------
-- 9.2.1 Standard VHDL Mathematical Packages
----------------------------------------------------------------

----------------------------------------------------------------
-- Real Number Mathematical Package
----------------------------------------------------------------

-- Page 298

procedure uniform ( variable seed1, seed2 : inout positive;
                    variable x : out real);

-- Example 9.2, Page 298

use ieee.numeric_bit.all;
subtype ALU_func is unsigned(3 downto 0);
subtype data_word is unsigned(15 downto 0);
...

entity ALU is
  port ( a, b : in data_word; func : in ALU_func;
         result : out data_word; carry : out bit );
end entity ALU;

architecture random_test of test_ALU is

  use ieee.numeric_bit.all;
  use ieee.math_real.uniform;

  signal a, b, result : data_word;
  signal func : ALU_func;
  signal carry : bit;

begin

  dut : entity work.ALU(structural)
    port map ( a, b, func, result, carry );

  stimulus : process is
    variable seed1, seed2 : positive := 1;
    variable a_real, b_real, func_real : real;
  begin
    wait for 100 ns;
    uniform ( seed1, seed2, a_real );
    uniform ( seed1, seed2, b_real );
    uniform ( seed1, seed2, func_real );
    a <= to_unsigned(
           natural(a_real
                   * real(2**integer'(data_word'length)) - 0.5),
           data_word'length );
    b <= to_unsigned(
           natural(b_real
                   * real(2**integer'(data_word'length)) - 0.5),
           data_word'length );
    func <= to_unsigned(
           natural(func_real
                   * real(2**integer'(ALU_func'length)) - 0.5),
           ALU_func'length );
  end process stimulus;

  ... --verification process to check result and carry

end architecture random_test;

----------------------------------------------------------------
-- Complex Number Mathematical Package
----------------------------------------------------------------

-- Page 299

type complex is record
    re : real;    -- Real part
    im : real;    -- Imaginary part
  end record;

subtype positive_real is real range 0.0 to real'high;
subtype principal_value is real range -math_pi to math_pi;

type complex_polar is record
    mag : positive_real;    -- Magnitude
    arg : principal_value;  -- Angle in radians; -math_pi is illegal
  end record;

----------------------------------------------------------------
-- 9.2.2 The std_logic_1164 Multivalue Logic System
----------------------------------------------------------------

----------------------------------------------------------------
-- 9.2.3 Standard Integer Numeric Packages
----------------------------------------------------------------

-- Page 305

type unsigned is array ( natural range <> ) of bit;
type signed is array ( natural range <> ) of bit;

type unresolved_unsigned is array (natural range <>) of std_ulogic;
type unresolved_signed   is array (natural range <>) of std_ulogic;

alias u_unsigned is unresolved_unsigned;
alias u_signed   is unresolved_signed;

subtype unsigned is (resolved) unresolved_unsigned;
subtype signed   is (resolved) unresolved_signed;

signal head_position : signed ( 0 to 15 );

subtype address is unsigned ( 31 downto 0 );
signal next_PC : address;
constant PC_increment : unsigned := X"4";

-- Example 9.3, Page 307

signal a, b, sum : unsigned(15 downto 0);
signal c_out : std_ulogic;

-- Example 9.3, Page 308

(c_out, sum) <= ('0' & a) + ('0' & b);

-- Page 308

signal a, b : unsigned(15 downto 0);
signal sum : unsigned(16 downto 0);
signal c_in;
...

sum <= ('0' & a) + ('0' & b) + c_in;

-- Example 9.4, Page 308

signal inc_en : std_ulogic;
signal inc_reg : unsigned(7 downto 0);
...

inc_reg_proc : process (clk) is
begin
  if rising_edge(clk) then
    inc_reg <= inc_reg + inc_en;
  end if;
end process inc_reg_proc;

if inc_en = '1' then
  inc_reg <= inc_reg + 1;
end if;

-- Page 312

context ieee_bit_context is
  library ieee;
  use ieee.numeric_bit.all;
end context ieee_bit_context;

context ieee_std_context is
  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
end context ieee_std_context;

----------------------------------------------------------------
-- 9.2.4 Standard Fixed-Point Packages
----------------------------------------------------------------

-- Page 314

type unresolved_ufixed is array (integer range <>) of std_ulogic;

alias u_ufixed is unresolved_ufixed;

subtype ufixed is (resolved) unresolved_ufixed;

-- Page 315

signal A : ufixed(3 downto -3) := "0110100";

variable X : ufixed(9 downto 2);
variable Y : ufixed(-5 downto -14);

type unresolved_sfixed is array (integer range <>) of std_ulogic;

alias u_sfixed is unresolved_sfixed;

subtype sfixed is (resolved) unresolved_sfixed;

signal S : sfixed(3 downto -3);

signal A4_2 : ufixed(3 downto -2);
signal B3_3 : ufixed(2 downto -3);
signal Y5_3 : ufixed(4 downto -3);
...

Y5_3 <= A4_2 + B3_3;

-- Page 316

signal A4 : ufixed(3 downto -3);
...

A4 <= "0110100";  -- string literal for 6.5

A4 <= to_ufixed(6.5, 3, -3);  -- pass indices

A4 <= to_ufixed(6.5, A4);  -- sized by A4

subtype ufixed4_3 is ufixed(3 downto -3);
signal A4, B4 : ufixed4_3;
signal Y5 : ufixed (4 downto -3);
...

Y5 <= A4 + "0110100";             -- illegal
Y5 <= A4 + ufixed4_3'("0110100");
Y5 <= A4 + 6.5;                   -- overloading with real
Y5 <= A4 + 6;                     -- overloading with integer

-- Page 317

signal A4_3 : ufixed(3 downto -3);
signal Y7_3 : ufixed(6 downto -3);
...

Y7_3 <= Y7_3 + A4_3;   -- illegal, result too big

Y7_3 <= resize(arg            => Y7_3 + A4_3,
               size_res       => Y7_3,
               overflow_style => fixed_wrap,
               round_style    => fixed_truncate);

Y7_3 <= resize (arg         => Y7_3 + A4_3,
                left_index  => 7,
                right_index => -3);

signal A4, B4, C4, D4 : ufixed(3 downto 0);
signal Y6             : ufixed(5 downto 0);
signal Y7A, Y7B       : ufixed(6 downto 0);
...

Y6 <= (A4 + B4) + (C4 + D4);

Y7A <= ((A4 + B4) + C4) + D4;

Y7B <= A4 + B4 + C4 + D4;

-- Page 318

constant x : ufixed(3 downto -8) := "010000110101";

----------------------------------------------------------------
-- 9.2.5 Standard Floating-Point Packages
----------------------------------------------------------------

-- Page 319

type unresolved_float is array (integer range <>) of std_ulogic;

-- Page 320

alias u_float is unresolved_float;

subtype float is (resolved) unresolved_float;

signal A : float(8 downto -23)
              := "01000000110100000000000000000000";

subtype unresolved_float32 is unresolved_float(8 downto -23);

subtype unresolved_float64 is unresolved_float(11 downto -52);

subtype unresolved_float128 is
          unresolved_float (15 downto -112);

-- Page 321

signal A32, B32, Y32 : float(8 downto -23);
...

Y32 <= A32 + B32;

-- Page 322

signal A_fp32 : float32;
...

A_fp32 <= "01000000110100000000000000000000";
A_fp32 <= to_float(6.5, 8, -32);  -- pass sizes
A_fp32 <= to_float(6.5, A_fp32);  -- size using A_fp32

signal A, Y : float32;
...

Y <= A + "01000000110100000000000000000000";  -- illegal
Y <= A + float32'("01000000110100000000000000000000");
Y <= A + 6.5;        -- overloading with real
Y <= A + 6;          -- overloading with integer

constant x : float(6 downto -11) := "011101100010001110";

----------------------------------------------------------------
-- 9.2.6 Package Summary
----------------------------------------------------------------

----------------------------------------------------------------
-- Operator Overloading Summary
----------------------------------------------------------------

----------------------------------------------------------------
-- Conversion Function Summary
----------------------------------------------------------------

----------------------------------------------------------------
-- Strength Reduction Function Summary
----------------------------------------------------------------

-- Example 9.5, Page 335

ncs_x01 <= to_X01(ncs);

assert not is_X(ncs) report "ncs is X" severity error;

----------------------------------------------------------------
-- Exercises
----------------------------------------------------------------