----------------------------------------------------------------
-- Chapter 11 Aliases
----------------------------------------------------------------

----------------------------------------------------------------
-- 11.1 Aliases for Data Objects
----------------------------------------------------------------

-- Example 11.1, Page 355

use work.alu_types.all, work.io_types.all;

-- Example 11.1, Page 356

library ieee;  use ieee.std_logic_1164.all;
use work.alu_types.all, work.io_types.all;

architecture structural of controller_system is

  alias alu_data_width is work.alu_types.data_width;
  alias io_data_width is work.io_types.data_width;

  signal alu_in1, alu_in2,
         alu_result :
           std_ulogic_vector(0 to alu_data_width - 1);
  signal io_data : std_ulogic_vector(0 to io_data_width - 1);
  ...

begin

  ...

end architecture structural;

-- Page 356

type register_array is array (0 to 15) of bit_vector(31 downto 0);

type register_set is record
    general_purpose_registers : register_array;
    program_counter : bit_vector(31 downto 0);
    program_status : bit_vector(31 downto 0);
  end record;

variable CPU_registers : register_set;

alias PSW is CPU_registers.program_status;
alias PC is CPU_registers.program_counter;
alias GPR is CPU_registers.general_purpose_registers;

alias SP is CPU_registers.general_purpose_registers(15);

-- Page 357

alias SP is GPR(15);

alias interrupt_level is PSW(30 downto 26);

alias interrupt_level : bit_vector(4 downto 0) is PSW(30 downto 26);

type register_array is array (natural range <>) of bit_vector;
signal register_file : register_array(0 to 15)(31 downto 0);

-- Page 358

alias bigendian_register_file : register_array(open)(0 to 31) is
        register_file;

-- Example 11.2, Page 358

function "+" ( bv1, bv2 : bit_vector ) return bit_vector;

function "+" ( bv1, bv2 : bit_vector ) return bit_vector is

  alias norm1 : bit_vector(1 to bv1'length) is bv1;
  alias norm2 : bit_vector(1 to bv2'length) is bv2;

  variable result : bit_vector(1 to bv1'length);
  variable carry : bit := '0';

begin
  if bv1'length /= bv2'length then
    report "arguments of different length" severity failure;
  else
    for index in norm1'reverse_range loop
      result(index) := norm1(index) xor norm2(index) xor carry;
      carry := ( norm1(index) and norm2(index) )
            or ( carry and ( norm1(index) or norm2(index) ) );
    end loop;
  end if;
  return result;
end function "+";

-- Example 11.3, Page 359

type bv_vector is array (natural range <>) of bit_vector;

function find_first_difference ( s1, s2 : in bv_vector)
                               return natural is
  alias s1_norm : bv_vector(0 to s1'length - 1)
                           (0 to s1'element'length - 1) is s1;
  alias s2_norm : bv_vector(0 to s2'length - 1)
                           (0 to s2'element'length - 1) is s2;
  variable count : natural := 0;
begin
  assert s1'length = s2'length and
         s1'element'length = s2'element'length;
  for i in s1_norm'range loop
    for j in s1_norm'element'range loop
      exit when s1_norm(i)(j) /= s2_norm(i)(j);
      count := count + 1;
    end loop;
  end loop;
  return count;
end function find_first_difference;

-- Page 360

type bit_matrix is
  array (natural range <>, natural range <>) of bit;
signal s : bit_matrix(15 downto 0, 15 downto 0);
alias bigendian_s : bit_matrix(0 to 15, 0 to 15) is s;

----------------------------------------------------------------
-- 11.2 Aliases for Non-Data Items
----------------------------------------------------------------

-- Page 360

alias binary_string is bit_vector;

variable s1, s2 : binary_string(0 to 7);
...

s1 := s1 and not s2;

-- Page 361

type system_status is (idle, active, overloaded);

alias status_type is work.system_types.system_status;

procedure increment ( bv : inout bit_vector;  by : in integer := 1 );

procedure increment ( int : inout integer;  by : in integer := 1 );

alias bv_increment is
  work.arithmetic_ops.increment [ bit_vector, integer ];

alias int_increment is
  work.arithmetic_ops.increment [ integer, integer ];

alias "*" is "and" [ bit, bit return bit ];

alias "+" is "or" [ bit, bit return bit ];

alias "-" is "not" [ bit return bit ];

-- Page 362

s <= a * b + (-a) * c;

alias high is std.standard.'1' [ return bit ];

-- Example 11.4, Page 362

package DMA_controller_types_and_utilities is

  alias word is work.cpu_types.word;
  alias status_value is work.cpu_types.status_value;

  alias "+" is work.bit_vector_unsigned_arithmetic."+"
            [ bit_vector, bit_vector return bit_vector ];

  ...

end package DMA_controller_types_and_utilities;

architecture behavioral of DMA_controller is

  use work.DMA_controller_types_and_utilities.all;

begin

  behavior : process is

    variable address_reg0, address_reg1 : word;
    variable count_reg0, count_reg1 : word;
    ...

  begin
    ...
    address_reg0 := address_reg0 + X"0000_0004";
    ...
  end process behavior;

end architecture behavioral;

----------------------------------------------------------------
-- Exercises
----------------------------------------------------------------

-- Exercise 1

subtype byte is bit_vector(0 to 7);
type data_array is array (0 to 31) of byte;
type network_packet is record
    source, dest, flags : byte;
    payload : data_array;
    checksum : byte;
  end record network_packet;
variable received_packet : network_packet;

-- Exercise 4

entity reverser is
  port ( d_in : in std_ulogic_vector;
         d_out : out std_ulogic_vector );
end entity reverser;