----------------------------------------------------------------
-- Chapter 13 Components and Configurations
----------------------------------------------------------------

----------------------------------------------------------------
-- 13.1 Components
----------------------------------------------------------------

----------------------------------------------------------------
-- 13.1.1 Component Declarations
----------------------------------------------------------------

-- Page 418

component flipflop is
  generic ( Tprop, Tsetup, Thold : delay_length );
  port ( clk : in bit;  clr : in bit;  d : in bit;
         q : out bit );
end component flipflop;

----------------------------------------------------------------
-- 13.1.2 Component Instantiation
----------------------------------------------------------------

-- Example 13.1, Page 419

entity reg4 is
  port ( clk, clr : in bit;  d : in bit_vector(0 to 3);
         q : out bit_vector(0 to 3) );
end entity reg4;

architecture struct of reg4 is

  component flipflop is
    generic ( Tprop, Tsetup, Thold : delay_length );
    port ( clk : in bit;  clr : in bit;  d : in bit;
           q : out bit );
  end component flipflop;

begin

  bit0 : component flipflop
      generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
      port map ( clk => clk, clr => clr, d => d(0), q => q(0) );

  bit1 : component flipflop
      generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
      port map ( clk => clk, clr => clr, d => d(1), q => q(1) );

  bit2 : component flipflop
      generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
      port map ( clk => clk, clr => clr, d => d(2), q => q(2) );

  bit3 : component flipflop
      generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
      port map ( clk => clk, clr => clr, d => d(3), q => q(3) );

end architecture struct;

----------------------------------------------------------------
-- 13.1.3 Packaging Components
----------------------------------------------------------------

-- Example 13.2, Page 421

library ieee;  use ieee.std_logic_1164.all;

package serial_interface_defs is

  subtype reg_address_vector is std_ulogic_vector(1 downto 0);

  constant status_reg_address : reg_address_vector := B"00";
  constant control_reg_address : reg_address_vector := B"01";
  constant rx_data_register : reg_address_vector := B"10";
  constant tx_data_register : reg_address_vector := B"11";

  subtype data_vector is std_ulogic_vector(7 downto 0);

  ...    -- other useful declarations

  component serial_interface is
    port ( clock_phi1, clock_phi2 : in std_ulogic;
           serial_select : in std_ulogic;
           reg_address : in reg_address_vector;
           data : inout data_vector;
           interrupt_request : out std_ulogic;
           rx_serial_data : in std_ulogic;
           tx_serial_data : out std_ulogic );
  end component serial_interface;

end package serial_interface_defs;

library ieee;  use ieee.std_logic_1164.all;

use work.serial_interface_defs.all;

entity serial_interface is
  port ( clock_phi1, clock_phi2 : in std_ulogic;
         serial_select : in std_ulogic;
         reg_address : in reg_address_vector;
         data : inout data_vector;
         interrupt_request : out std_ulogic;
         rx_serial_data : in std_ulogic;
         tx_serial_data : out std_ulogic );
end entity serial_interface;

-- Example 13.2, Page 422

library ieee;  use ieee.std_logic_1164.all;

architecture structure of microcontroller is

  use work.serial_interface_defs.serial_interface;

  ...    -- declarations of other components, signals, etc

begin

  serial_a : component serial_interface
    port map ( clock_phi1 => buffered_phi1,
               clock_phi2 => buffered_phi2,
               serial_select => serial_a_select,
               reg_address => internal_addr(1 downto 0),
               data => internal_data_bus,
               interrupt_request => serial_a_int_req,
               rx_serial_data => rx_data_a,
               tx_serial_data => tx_data_a );

  ...    -- other component instances

end architecture structure;

----------------------------------------------------------------
-- 13.2 Configuring Component Instances
----------------------------------------------------------------

----------------------------------------------------------------
-- 13.2.1 Basic Configuration Declarations
----------------------------------------------------------------

-- Page 423

for bit0, bit1 : flipflop
  use entity work.edge_triggered_Dff(basic);
end for;

-- Example 13.3, Page 424

library star_lib;
use star_lib.edge_triggered_Dff;

configuration reg4_gate_level of reg4 is

  for struct  -- architecture of reg4

    for bit0 : flipflop
      use entity edge_triggered_Dff(hi_fanout);
    end for;

    for others : flipflop
      use entity edge_triggered_Dff(basic);
    end for;

  end for;  -- end of architecture struct

end configuration reg4_gate_level;

----------------------------------------------------------------
-- 13.2.2 Configuring Multiple Levels of Hierarchy
----------------------------------------------------------------

-- Page 425

for flag_reg : reg4
  use configuration work.reg4_gate_level;
end for;

-- Example 13.4, Page 425

subtype digit is bit_vector(3 downto 0);

use work.counter_types.digit;

entity counter is
  port ( clk, clr : in bit;
         q0, q1 : out digit );
end entity counter;

architecture registered of counter is

  component digit_register is
    port ( clk, clr : in bit;
           d : in digit;
           q : out digit );
  end component digit_register;

  signal current_val0, current_val1, next_val0, next_val1 : digit;

begin

  val0_reg : component digit_register
    port map ( clk => clk, clr => clr, d => next_val0,
               q => current_val0 );

  val1_reg : component digit_register
    port map ( clk => clk, clr => clr, d => next_val1,
               q => current_val1 );

  -- other component instances
  ...

end architecture registered;

-- Example 13.4, Page 426

configuration counter_down_to_gate_level of counter is

  for registered

    for all : digit_register
      use configuration work.reg4_gate_level;
    end for;

    ...    -- bindings for other component instances

  end for;  -- end of architecture registered

end configuration counter_down_to_gate_level;

-- Example 13.5, Page 427

library star_lib;
use star_lib.edge_triggered_Dff;

configuration full of counter is

  for registered  -- architecture of counter

    for all : digit_register
      use entity work.reg4(struct);

      for struct  -- architecture of reg4

        for bit0 : flipflop
          use entity edge_triggered_Dff(hi_fanout);
        end for;

        for others : flipflop
          use entity edge_triggered_Dff(basic);
        end for;

      end for;  -- end of architecture struct

    end for;

    ...  -- bindings for other component instances

  end for;  -- end of architecture registered

end configuration full;

----------------------------------------------------------------
-- 13.2.3 Direct Instantiation of Configured Entities
----------------------------------------------------------------

-- Example 13.6, Page 429

architecture top_level of alarm_clock is

  use work.counter_types.digit;

  signal reset_to_midnight, seconds_clk : bit;
  signal seconds_units, seconds_tens : digit;
  ...

begin

  seconds : configuration work.counter_down_to_gate_level
    port map ( clk => seconds_clk, clr => reset_to_midnight,
               q0 => seconds_units, q1 => seconds_tens );

  ...

end architecture top_level;

----------------------------------------------------------------
-- 13.2.4 Generic and Port Maps in Configurations
----------------------------------------------------------------

-- Example 13.7, Page 430

library ieee;  use ieee.std_logic_1164.all;

entity reg is
  generic ( t_setup, t_hold, t_pd : delay_length;
            width : positive );
  port ( clock : in std_ulogic;
         data_in : in std_ulogic_vector(0 to width - 1);
         data_out : out std_ulogic_vector(0 to width - 1) );
end entity reg;

architecture structural of controller is

  component reg is
    generic ( width : positive );
    port ( clock : in std_ulogic;
           data_in : in std_ulogic_vector(0 to width - 1);
           data_out : out std_ulogic_vector(0 to width - 1) );
  end component reg;

  ...

begin

  state_reg : component reg
    generic map ( width => state_type'length )
    port map ( clock => clock_phase1,
               data_in => next_state,
               data_out => current_state );

  ...

end architecture structural;

-- Example 13.7, Page 431

configuration controller_with_timing of controller is

  for structural

    for state_reg : reg
      use entity work.reg(gate_level)
      generic map ( t_setup => 200 ps, t_hold => 150 ps,
                    t_pd => 150 ps, width => width );
    end for;

    ...

  end for;

end configuration controller_with_timing;

-- Example 13.8, Page 431

architecture structure of computer_system is

  component decoder_2_to_4 is
    generic ( prop_delay : delay_length );
    port ( in0, in1 : in bit;
           out0, out1, out2, out3 : out bit );
  end component decoder_2_to_4;

  ...

begin

  interface_decoder : component decoder_2_to_4
    generic map ( prop_delay => 4 ns )
    port map ( in0 => addr(4), in1 => addr(5),
               out0 => interface_a_select,
               out1 => interface_b_select,
               out2 => interface_c_select,
               out3 => interface_d_select );

  ...

end architecture structure;

-- Example 13.8, Page 432

entity decoder_3_to_8 is
  generic ( Tpd_01, Tpd_10 : delay_length );
  port ( s0, s1, s2 : in bit;
         enable : in bit;
         y0, y1, y2, y3, y4, y5, y6, y7 : out bit );
end entity decoder_3_to_8;

configuration computer_structure of computer_system is

  for structure

    for interface_decoder : decoder_2_to_4
      use entity work.decoder_3_to_8(basic)
      generic map ( Tpd_01 => prop_delay, Tpd_10 => prop_delay )
      port map ( s0 => in0, s1 => in1, s2 => '0',
                 enable => '1',
                 y0 => out0, y1 => out1, y2 => out2, y3 => out3,
                 y4 => open, y5 => open, y6 => open, y7 => open );
    end for;

    ...

  end for;

end configuration computer_structure;

-- Page 434

component nand3 is
  port ( a, b, c : in bit := '1';  y : out bit );
end component nand3;

gate1 : component nand3
  port map ( a => s1, b => s2, c => open, y => s3 );

entity nand2 is
  port ( a, b : in bit := '1';  y : out bit );
end entity nand2;

-- Page 435

for gate1 : nand3
  use entity work.nand2(basic);
end for;

----------------------------------------------------------------
-- 13.2.5 Deferred Component Binding
----------------------------------------------------------------

-- Example 13.9, Page 435

architecture structural of single_board_computer is

  ...  -- type and signal declarations

  component processor is
    port ( clk : in bit;  a_d : inout word; ... );
  end component processor;

  component memory is
    port ( addr : in bit_vector(25 downto 0); ... );
  end component memory;

  component serial_interface is
    port ( clk : in bit;
           address : in bit_vector(3 downto 0); ... );
  end component serial_interface;

begin

  cpu : component processor
    port map ( clk => sys_clk, a_d => cpu_a_d, ... );

  main_memory : component memory
    port map ( addr => latched_addr(25 downto 0), ... );

  serial_interface_a : component serial_interface
    port map ( clk => sys_clk,
               address => latched_addr(3 downto 0), ... );

  ...

end architecture structural;

-- Example 13.9, Page 436

library chips;

configuration intermediate of single_board_computer is

  for structural

    for cpu : processor
      use entity chips.XYZ3000_cpu(full_function)
      port map ( clock => clk, addr_data => a_d, ... );
    end for;

    for main_memory : memory
      use entity work.memory_array(behavioral);
    end for;

    for all : serial_interface
      use open;
    end for;

    ...

  end for;

end configuration intermediate;

----------------------------------------------------------------
-- 13.3 Configuration Specifications
----------------------------------------------------------------

-- Example 13.10, Page 437

entity nand3 is
  port ( a, b, c : in bit;  y : out bit );
end entity nand3;

-- Example 13.10, Page 438

library gate_lib;

architecture ideal of logic_block is

  component nand2 is
    port ( in1, in2 : in bit;  result : out bit );
  end component nand2;

  for all : nand2
    use entity gate_lib.nand3(behavioral)
    port map ( a => in1, b => in2, c => '1', y => result );
  end for;

  ...  -- other declarations

begin

  gate1 : component nand2
    port map ( in1 => s1, in2 => s2, result => s3 );

  ...  -- other concurrent statements

end architecture ideal;

-- Page 438

for all : nand2
  use entity gate_lib.nand3(behavioral)
  port map ( a => in1, b => in2, c => '1', y => result );

----------------------------------------------------------------
-- 13.3.1 Incremental Binding
----------------------------------------------------------------

-- Example 13.11, Page 439

architecture structural of control_section is

  component reg is
    generic ( width : positive );
    port ( clk : in std_ulogic;
           d : in std_ulogic_vector(0 to width - 1);
           q : out std_ulogic_vector(0 to width - 1) );
  end component reg;

  for flag_reg : reg
    use entity work.reg(gate_level)
    port map ( clock => clk, data_in => d, data_out => q );
  end for;

  ...

begin

  flag_reg : component reg
    generic map ( width => 3 )
    port map ( clk => clock_phase1,
               d(0) => zero_result, d(1) => neg_result,
               d(2) => overflow_result,
               q(0) => zero_flag, q(1) => neg_flag,
               q(2) => overflow_flag );

  ...

end architecture structural;

-- Example 13.11, Page 440

library ieee;  use ieee.std_logic_1164.all;

entity reg is
  generic ( t_setup, t_hold, t_pd : delay_length;
            width : positive );
  port ( clock : in std_ulogic;
         reset_n : in std_ulogic := 'H';
         data_in : in std_ulogic_vector(0 to width - 1);
         data_out : out std_ulogic_vector(0 to width - 1) );
end entity reg;

configuration controller_with_timing of control_section is

  for structural

    for flag_reg : reg
      generic map ( t_setup => 200 ps, t_hold => 150 ps,
                    t_pd => 150 ps, width => width )
      port map ( reset_n => '1' );
    end for;

    ...

  end for;

end configuration controller_with_timing;

-- Example 13.12, Page 441

architecture detailed_timing of interlock_control is

  component nor_gate is
    generic ( input_width : positive );
    port ( input : in std_ulogic_vector(0 to input_width - 1);
           output : out std_ulogic );
  end component nor_gate;

  for ex_interlock_gate : nor_gate
    use entity cell_lib.nor_gate(primitive)
    generic map ( width => input_width,
                  Tpd01 => 250 ps, Tpd10 => 200 ps );  -- estimates
  end for;

  ...

begin

  ex_interlock_gate : component nor_gate
    generic map ( input_width => 2 )
    port map ( input(0) => reg_access_hazard,
               input(1) => load_hazard,
               output => stall_ex_n);

  ...

end architecture detailed_timing;

configuration interlock_control_with_estimates
  of interlock_control is

  for detailed_timing

  end for;

  ...

end configuration interlock_control_with_estimates;

-- Example 13.12, Page 442

configuration interlock_control_with_actual
  of interlock_control is

  for detailed_timing

    for ex_interlock_gate : nor_gate
      generic map ( Tpd01 => 320 ps, Tpd10 => 230 ps );
    end for;

    ...

  end for;

end configuration interlock_control_with_actual;

-- Example 13.13, Page 442

architecture gate_level of misc_logic is

  component nand3 is
    generic ( Tpd : delay_length );
    port ( a, b, c : in bit;  y : out bit );
  end component nand3;

  for all : nand3
    use entity project_lib.nand3(basic);
  end for;
  
  ...

begin

  gate1 : component nand3
    generic map ( Tpd => 2 ns )
    port map ( a => sig1, b => sig2, c => sig3, y => out_sig );

  ...

end architecture gate_level;

-- Example 13.13, Page 443

configuration misc_logic_reconfigured of misc_logic is

  for gate_level

    for gate1 : nand3
      generic map ( Tpd => 1.6 ns )
      port map ( a => c, c => a, b => b, y => y );
    end for;

  end for;

end configuration misc_logic_reconfigured;

----------------------------------------------------------------
-- Exercises
----------------------------------------------------------------

-- Exercise 5

architecture register_transfer of digital_filter is
  ...
  component multiplier is
    port ( ... );
  end component multiplier;
begin
  coeff_1_multiplier : component multiplier
    port map ( ... );
  ...
end architecture register_transfer;

-- Exercise 8

component multiplexer is
  port ( s, d0, d1 : in bit; z : out bit );
end component multiplexer;
...

serial_data_mux : component multiplexer
  port map ( s => serial_source_select,
             d0 => rx_data_0, d1 => rx_data_1,
             z => internal_rx_data );

entity multiplexer is
  generic ( Tpd : delay_length := 3 ns );
  port ( s, d0, d1 : in bit; z : out bit );
end entity multiplexer;

-- Exercise 10

entity nand4 is
  generic ( Tpd_01, Tpd_10 : delay_length := 2 ns );
  port ( a, b, c, d : in bit := '1'; y : out bit );
end entity nand4;

for gate1 : nand3
  use entity get_lib.nand4(basic);
end for;

-- Exercise 18

entity XYZ1234A is
  generic ( T_phi_out, T_d_z : delay_length;
            debug_trace : boolean := false );
  port ( phi1, phi2 : in std_ulogic;   -- 2 phase clock
         cs : in std_ulogic;           -- chip select
         a : in std_ulogic_vector(1 downto 0);     -- address
         d : inout std_ulogic_vector(1 downto 0);  -- data
         int_req : out std_ulogic;     -- interrupt
         rx_d : in std_ulogic;         -- rx serial data
         tx_d : out std_ulogic );      -- tx serial data
end entity XYZ1234A;