----------------------------------------------------------------
-- Chapter 20 Attributes and Groups
----------------------------------------------------------------

----------------------------------------------------------------
-- 20.1 Predefined Attributes
----------------------------------------------------------------

----------------------------------------------------------------
-- 20.1.1 Attributes of Scalar Types
----------------------------------------------------------------

----------------------------------------------------------------
-- 20.1.2 Attributes of Array Types and Objects
----------------------------------------------------------------

----------------------------------------------------------------
-- 20.1.3 Attributes Giving Types
----------------------------------------------------------------

----------------------------------------------------------------
-- 20.1.4 Attributes of Signals
----------------------------------------------------------------

----------------------------------------------------------------
-- 20.1.5 Attributes of Named Items
----------------------------------------------------------------

-- Page 607

utilities.utility_definitions.word_size'simple_name

-- Example 20.1, Page 608

architecture behavior of flipflop is
begin

  timing_check : process (clk) is
  begin
    if clk = '1' then
      assert d'last_event >= Tsetup
        report "set up violation detected in "
               & timing_check'path_name
        severity error;
    end if;
  end process timing_check;

  ...  -- functionality

end architecture behavior;

-- Example 20.2, Page 609

package mem_pkg is

  subtype word is bit_vector(0 to 31);
  type word_array is array (natural range <>) of word;

  procedure load_array ( words : out word_array;
                         file_name : string );

end package mem_pkg;

package body mem_pkg is

  procedure load_array ( words : out word_array;
                         file_name : string ) is
    -- words'path_name = ":project:mem_pkg:load_array:words"

    use std.textio.all;
    file load_file : text open read_mode is file_name;
    -- load_file'path_name
    --   = ":project:mem_pkg:load_array:load_file"

    procedure read_line is
    -- read_line'path_name
    --   = ":project:mem_pkg:load_array:read_line:"
      variable current_line : line;
      -- current_line'path_name
      --   = ":project:mem_pkg:load_array:read_line:current_line"
    begin
      ...
    end procedure read_line;

  begin  -- load_array
    ...
  end procedure load_array;

end package body mem_pkg;

-- Example 20.3, Page 610

package counter_pkg is

  type counter is protected
    procedure increment;
    ...
  end protected counter;

end package counter_pkg;

package body counter_pkg is

  type counter is protected body

    constant limit : natural := 100;
    variable count : natural := 0;

    procedure increment is
    begin
      assert count < limit
        report "Counter overflow in " & increment'path_name;
      count := (count + 1) mod limit;
    end procedure increment;

    ...

  end protected body counter;

end package body counter_pkg;

-- Example 20.3, Page 611

library project_lib;
package system_counter_pkg is
  use project_lib.counter_pkg.all;
  shared variable test_counter, event_counter : counter;
end package system_counter_pkg;

-- Example 20.4, Page 612

entity top is
end entity top;

--------------------------------------------------

architecture top_arch of top is

  signal top_sig : ...;                  -- 1

begin

  stimulus : process is
    variable var : ...;                  -- 2
  begin
    ...
  end process stimulus;

  rep_gen : for index in 0 to 7 generate
  begin

    end_gen : if index = 7 generate
      signal end_sig : ...;              -- 3
    begin
      ...
    end generate end_gen;

    other_gen : if index /= 7 generate
      signal other_sig : ...;            -- 4
    begin
      other_comp : entity work.bottom(bottom_arch)
        port map ( ... );
    end generate other_gen;

  end generate rep_gen;

end architecture top_arch;

-- Example 20.4, Page 614

entity bottom is
  port ( ... );
end entity bottom;

--------------------------------------------------

architecture bottom_arch of bottom is

  signal bot_sig : ...;             -- 5

  procedure proc ( ... ) is
    variable v : ...;               -- 6
  begin
    ...
  end procedure proc;

begin

  delays : block is
    constant d : integer := 1;      -- 7
  begin
    ...
  end block delays;

  func : block is
  begin

    process is
      variable v : ...;             -- 8
    begin
      ...
    end process;

  end block func;

end architecture bottom_arch;

----------------------------------------------------------------
-- 20.2 User-Defined Attributes
----------------------------------------------------------------

----------------------------------------------------------------
-- 20.2.1 Attribute Declarations
----------------------------------------------------------------

-- Page 616

attribute cell_name : string;
attribute pin_number : positive;
attribute max_wire_delay : delay_length;
attribute encoding : bit_vector;

type length is range 0 to integer'high
  units nm;
    um = 1000 nm;
    mm = 1000 um;
    mil = 25400 nm;
  end units length;

type coordinate is record
    x, y : length;
  end record coordinate;

attribute cell_position : coordinate;

----------------------------------------------------------------
-- 20.2.2 Attribute Specifications
----------------------------------------------------------------

-- Page 617

attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
attribute pin_number of enable : signal is 14;
attribute max_wire_delay of clk : signal is 50 ps;
attribute encoding of idle_state : literal is b"0000";
attribute cell_position of the_fpu : label is ( 540 um, 1200 um );

type string_vector is array (positive range <>) of string;
attribute key_vector : string_vector;

attribute key_vector of e : entity is
("66A6D 7DF3A 88CE1 8DEEB", "012BD 2BEE9 98634 93FE1");

-- Page 618

architecture std_cell of flipflop is

  attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";

  ...  -- other declarations

begin
  ...
end architecture std_cell;

package model_utilities is

  attribute optimize : string;
  attribute optimize of model_utilities : package is "level_4";

  ...

end package model_utilities;

-- Example 20.5, Page 619

process is

  procedure add_with_overflow ( a, b : in integer;
                                sum : out integer;
                                overflow : out boolean ) is ...

  procedure add_with_overflow ( a, b : in bit_vector;
                                sum : out bit_vector;
                                overflow : out boolean ) is ...

  attribute built_in : string;

  attribute built_in of
    add_with_overflow [ integer, integer,
                        integer, boolean ] : procedure is
    "int_add_overflow";

  attribute built_in of
    add_with_overflow [ bit_vector, bit_vector,
                        bit_vector, boolean ] : procedure is
    "bit_vector_add_overflow";

begin
  ...
end process;

-- Page 619

function "&" ( a, b : stimulus_list ) return stimulus_list;

attribute debug : string;
attribute debug of "&" [ stimulus_list, stimulus_list
                         return stimulus_list ] : function is
                   "source_statement_step";

-- Page 620

procedure add ( a, b : in integer; s : out integer );
procedure add ( a, b : in real; s : out real );
function add ( a, b : integer ) return integer;
function add ( a, b : real ) return real;

attribute built_in : boolean;
atribute built_in of add : procedure is true;
attribute built_in of add : function is false;

type mvl is ('X', '0', '1', 'Z');
type mvl_vector is array ( integer range <>) of mvl;
function resolve_mvl ( drivers : mvl_vector ) return mvl;

subtype resolved_mvl is resolve_mvl mvl;

type builtin_types is (builtin_bit, builtin_mvl, builtin_integer);
attribute builtin : builtin_types;

attribute builtin of resolved_mvl : subtype is builtin_mvl;

-- Example 20.6, Page 620

attribute layout_ignore : boolean;
attribute pin_number : positive;

library ieee;  use ieee.std_logic_1164.all;
use work.physical_attributes.all;

entity \74x138\ is
  generic ( Tpd : time );
  port ( en1, en2a_n, en2b_n : in std_ulogic;
         s0, s1, s2 : in std_ulogic;
         y0, y1, y2, y3, y4, y5, y6, y7 : out std_ulogic );

  attribute layout_ignore of Tpd : constant is true;

  attribute pin_number of s0 : signal is 1;
  attribute pin_number of s1 : signal is 2;
  attribute pin_number of s2 : signal is 3;
  attribute pin_number of en2a_n : signal is 4;
  ...

end entity \74x138\;

-- Example 20.7, Page 621

procedure mem_read ( address : in natural;
                     result : out byte_vector;
                     signal memory_bus : inout ram_bus ) is

  attribute trace of address : constant is "integer/hex";
  attribute trace of result : variable is "byte/multiple/hex";
  attribute trace of memory_bus : signal is
                     "custom/command=rambus.cmd";
  ...

begin
  ...
end procedure mem_read;

-- Example 20.8, Page 622

library ieee;  use ieee.std_logic_1164.all;
library graphics;

package gate_components is

  use graphics.graphics_pkg.graphic_symbol,
      graphics.graphics_pkg.graphic_style;

  component and2 is
    generic ( prop_delay : delay_length );
    port ( a, b : in std_ulogic;  y : out std_ulogic );
  end component and2;

  attribute graphic_symbol of and2 : component is "and2";
  attribute graphic_style of and2 : component is
                             "color:default, weight:bold";

  ...

end package gate_components;

-- Example 20.9, Page 622

architecture cell_based of CPU is

  component fpu is
    port ( ... );
  end component;

  use work.cell_attributes.all;

  attribute cell_position of the_fpu : label is ( 540 um, 1200 um );

  ...

begin

  the_fpu : component fpu
    port map ( ... );

  ...

end architecture cell_based;

-- Example 20.10, Page 623

controller : process is

  attribute synthesis_hint of control_loop : label is
                              "implementation:FSM(clk)";
  ...

begin
  ...  -- initialization
  control_loop : loop
    wait until clk = '1';
    ...
  end loop;
end process controller;

-- Example 20.11, Page 623

type controller_state is (idle, active, fail_safe);
type load_level is (idle, busy, overloaded);

-- Example 20.11, Page 624

attribute encoding of
  idle [ return controller_state ] : literal is b"00";
attribute encoding of
  active [ return controller_state ] : literal is b"01";
attribute encoding of
  fail_safe [ return controller_state ] : literal is b"10";

-- Example 20.12, Page 624

package voltage_defs is

  type voltage is range -2e9 to +2e9
    units
      nV;
      uV = 1000 nV;
      mV = 1000 uV;
      V = 1000 mV;
    end units voltage;

  attribute resolution : real;

  attribute resolution of nV : units is 1.0;
  attribute resolution of uV : units is 0.01;
  attribute resolution of mV : units is 0.01;
  attribute resolution of V : units is 0.001;

end package voltage_defs;

-- Page 624

property SingleCycleRequest is
  always req -> next not req;

sequence ReadCycle is
  { ba; {bb[*]} && {ar[->]; dr[->]}; not bb };

attribute enable_heuristics of
            SingleCycleRequest : propery is true;
attribute enable_heuristics of ReadCycle : sequence is true;

-- Example 20.13, Page 625

library ieee;  use ieee.std_logic_1164.all;
use work.timing_attributes.all;

architecture structural of sequencer is

  signal recovered_clk1, recovered_clk2 : std_ulogic;
  signal test_enable : std_ulogic;
  signal test_data : std_ulogic_vector(0 to 15);

  attribute max_wire_delay of
    recovered_clk1, recovered_clk2 : signal is 100 ps;

  attribute max_wire_delay of others : signal is 200 ps;

  ...

begin
  ...
end architecture structural;

-- Page 626

attribute cell_allocation of
  mult : label is "wallace_tree_multiplier";
attribute cell_position of
  mult : label is ( 1200 um, 4500 um );
attribute cell_orientation of
  mult : label is down;

std_cell'cell_name
enable'pin_number
clk'max_wire_delay
idle_state'encoding
the_fpu'cell_position

increment [ bit_vector return bit_vector ] 'built_in
increment [ std_ulogic_vector return std_ulogic_vector ] 'built_in

high [ return speed_range ] 'representation
high [ return coolant_level ] 'representation

-- Page 627

c1 : entity work.e(arch)
  port map ( p => s );

----------------------------------------------------------------
-- 20.3 Groups
----------------------------------------------------------------

-- Page 628

group signal_pair is (signal, signal);

group clock_pair : signal_pair ( clk_phase1, clk_phase2 );

attribute max_skew : time;

-- Page 629

attribute max_skew of clock_pair : group is 200 ps;

-- Example 20.14, Page 629

group component_instances is ( label <> );

group U1 : component_instances ( nand1, nand2, nand3 );
group U2 : component_instances ( inv1, inv2 );

attribute IC_allocation : string;

attribute IC_allocation of U1 : group is "74LS00";
attribute IC_allocation of U2 : group is "74LS04";

-- Example 20.15, Page 629

group port_pair is ( signal, signal );

attribute max_prop_delay : time;

-- Example 20.15, Page 630

library ieee;  use ieee.std_logic_1164.all;
use work.constraints.port_pair, work.constraints.max_prop_delay;

entity clock_buffer is
  port ( clock_in : in std_ulogic;
         clock_out1, clock_out2, clock_out3 : out std_ulogic );

  group clock_to_out1 : port_pair ( clock_in, clock_out1 );
  group clock_to_out2 : port_pair ( clock_in, clock_out2 );
  group clock_to_out3 : port_pair ( clock_in, clock_out3 );

  attribute max_prop_delay of clock_to_out1 : group is 2 ns;
  attribute max_prop_delay of clock_to_out2 : group is 2 ns;
  attribute max_prop_delay of clock_to_out3 : group is 2 ns;

end entity clock_buffer;

----------------------------------------------------------------
-- Exercises
----------------------------------------------------------------

-- Exercise 2

dut : entity work.counter(registered)
  port map ( ... );

-- Exercise 3

type capacitance is range 0 to integer'high
  units pF;
  end units capacitance;

-- Exercise 5

attribute optimization : string;

procedure test_empty ( variable list : in list_ptr;
                       is_empty : out boolean ) is ...

-- Exercise 6

step_1 : a := b * c + k;
step_2 : n := a + 4 * j;